Intel ARCHITECTURE IA-32 User Manual download pdf (Page 451)

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Vol. 3A 10-11

MEMORY CACHE CONTROL

• Cache control and memory ordering instructions — The IA-32 architecture provides

several instructions that control the caching of data, the ordering of memory reads and

writes, and the prefetching of data. These instructions allow software to control the

caching of specific data structures, to control memory coherency for specific locations in

memory, and to force strong memory ordering at specific locations in a program.

The following sections describe these two groups of cache control mechanisms.

10.5.1 Cache Control Registers and Bits

The current IA-32 architecture provides the following cache-control registers and bits for use in

enabling and/or restricting caching to various pages or regions in memory (see Figure 10-2):

• CD flag, bit 30 of control register CR0 — Controls caching of system memory locations

(see Section 2.5, “Control Registers”). If the CD flag is clear, caching is enabled for the

whole of system memory, but may be restricted for individual pages or regions of memory

by other cache-control mechanisms. When the CD flag is set, caching is restricted in the

processor’s caches (cache hierarchy) for the Pentium 4, Intel Xeon, and P6 family

processors and prevented for the Pentium processor (see note below). With the CD flag set,

however, the caches will still respond to snoop traffic. Caches should be explicitly flushed

to insure memory coherency. For highest processor performance, both the CD and the NW

flags in control register CR0 should be cleared. Table 10-5 shows the interaction of the CD

and NW flags.

The effect of setting the CD flag is somewhat different for the Pentium 4, Intel Xeon,

and P6 family processors than for the Pentium processor (see Table 10-5). To insure

memory coherency after the CD flag is set, the caches should be explicitly flushed (see

Section 10.5.3, “Preventing Caching”). Setting the CD flag for the Pentium 4, Intel

Xeon, and P6 family processors modifies cache line fill and update behaviour. Also for

the Pentium 4, Intel Xeon, and P6 family processors, setting the CD flag does not force

strict ordering of memory accesses unless the MTRRs are disabled and/or all memory is

referenced as uncached (see Section 7.2.4, “Strengthening or Weakening the Memory

Ordering Model”).

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