Intel ARCHITECTURE IA-32 User Manual download pdf (Page 345)

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101

Vol. 3A 8-21

ADVANCED PROGRAMMABLE INTERRUPT CONTROLLER (APIC)

The time base for the timer is derived from the processor’s bus clock, divided by the value spec-

ified in the divide configuration register.

The timer can be configured through the timer LVT entry for one-shot or periodic operation. In

one-shot mode, the timer is started by programming its initial-count register. The initial count

value is then copied into the current-count register and count-down begins. After the timer

reaches zero, an timer interrupt is generated and the timer remains at its 0 value until repro-

grammed.

In periodic mode, the current-count register is automatically reloaded from the initial-count

repeated. If during the count-down process the initial-count register is set, counting will restart,

using the new initial-count value. The initial-count register is a read-write register; the current-

count register is read only.

The LVT timer register determines the vector number that is delivered to the processor with the

timer interrupt that is generated when the timer count reaches zero. The mask flag in the LVT

timer register can be used to mask the timer interrupt.

Figure 8-10. Divide Configuration Register

Figure 8-11. Initial Count and Current Count Registers

Address: FEE0 03E0H

Value after reset: 0H

Divide Value (bits 0, 1 and 3)

000: Divide by 2

001: Divide by 4

010: Divide by 8

011: Divide by 16

100: Divide by 32

101: Divide by 64

110: Divide by 128

111: Divide by 1

Reserved

1234

Initial Count

Address: Initial Count

Value after reset: 0H

Current Count

Current Count FEE0 0390H

FEE0 0380H

1 2 ... 340 341 342 343 344 345 346 347 348 349 350 ... 635 636

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Intel ARCHITECTURE IA-32 User Manual Page 345

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