Intel ARCHITECTURE IA-32 User Manual download pdf (Page 285)

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Vol. 3A 7-17

MULTIPLE-PROCESSOR MANAGEMENT

• All devices in the system that are capable of delivering interrupts to the processors must be

inhibited from doing so for the duration of the MP initialization protocol. The time during

which interrupts must be inhibited includes the window between when the BSP issues an

INIT-SIPI-SIPI sequence to an AP and when the AP responds to the last SIPI in the

sequence.

7.5.3 MP Initialization Protocol Algorithm for

Intel Xeon Processors

Following a power-up or RESET of an MP system, the Intel Xeon processors in the system

execute the MP initialization protocol algorithm to initialize each of the logical processors on

the system bus. In the course of executing this algorithm, the following boot-up and initializa-

tion operations are carried out:

1. Each logical processor on the system bus is assigned a unique 8-bit APIC ID, based on

system topology (see Section 7.5.5, “Identifying Logical Processors in an MP System”).

This ID is written into the local APIC ID register for each processor.

2. Each logical processor is assigned a unique arbitration priority based on its APIC ID.

3. Each logical processor executes its internal BIST simultaneously with the other logical

processors on the system bus.

4. Upon completion of the BIST, the logical processors use a hardware-defined selection

mechanism to select the BSP and the APs from the available logical processors on the

system bus. The BSP selection mechanism differs depending on the family, model, and

stepping IDs of the processors, as follows:

— Family, model, and stepping IDs of F0AH and onwards:

• The logical processors begin monitoring the BNR# signal, which is toggling.

When the BNR# pin stops toggling, each processor attempts to issue a NOP

special cycle on the system bus.

• The logical processor with the highest arbitration priority succeeds in issuing a

NOP special cycle and is nominated the BSP. This processor sets the BSP flag in

its IA32_APIC_BASE MSR, then fetches and begins executing BIOS boot-strap

code, beginning at the reset vector (physical address FFFF FFF0H).

• The remaining logical processors (that failed in issuing a NOP special cycle) are

designated as APs. They leave their BSP flags in the clear state and enter a “wait-

for-SIPI state.”

— Family, model, and stepping IDs up to F09H:

• Each processor broadcasts a BIPI to “all including self.” The first processor that

broadcasts a BIPI (and thus receives its own BIPI vector), selects itself as the BSP

and sets the BSP flag in its IA32_APIC_BASE MSR. (See Appendix C.1,

“Overview of the MP Initialization Process For P6 Family Processors,” for a

description of the BIPI, FIPI, and SIPI messages.)

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