Intel ARCHITECTURE IA-32 User Manual download pdf (Page 276)

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7-8 Vol. 3A

MULTIPLE-PROCESSOR MANAGEMENT

To allow optimizing of instruction execution, the IA-32 architecture allows departures from

strong-ordering model called processor ordering in Pentium 4, Intel Xeon, and P6 family

processors. These processor-ordering variations allow performance enhancing operations such

as allowing reads to go ahead of buffered writes. The goal of any of these variations is to increase

instruction execution speeds, while maintaining memory coherency, even in multiple-processor

systems.

The following sections describe the memory ordering models used by the Intel486 and Pentium

processors, and by the Pentium 4, Intel Xeon, and P6 family processors.

7.2.1 Memory Ordering in the Intel

Pentium

and Intel486™

Processors

The Pentium and Intel486 processors follow the processor-ordered memory model; however,

they operate as strongly-ordered processors under most circumstances. Reads and writes always

appear in programmed order at the system bus—except for the following situation where

processor ordering is exhibited. Read misses are permitted to go ahead of buffered writes on the

system bus when all the buffered writes are cache hits and, therefore, are not directed to the same

address being accessed by the read miss.

In the case of I/O operations, both reads and writes always appear in programmed order.

Software intended to operate correctly in processor-ordered processors (such as the Pentium 4,

Intel Xeon, and P6 family processors) should not depend on the relatively strong ordering of

the Pentium or Intel486 processors. Instead, it should insure that accesses to shared variables

that are intended to control concurrent execution among processors are explicitly required to

obey program ordering through the use of appropriate locking or serializing operations (see

Section 7.2.4, “Strengthening or Weakening the Memory Ordering Model”).

7.2.2 Memory Ordering Pentium 4, Intel

Xeon

, and P6 Family

Processors

The Pentium 4, Intel Xeon, and P6 family processors also use a processor-ordered memory

ordering model that can be further defined as “write ordered with store-buffer forwarding.” This

model can be characterized as follows.

In a single-processor system for memory regions defined as write-back cacheable, the following

ordering rules apply:

1. Reads can be carried out speculatively and in any order.

2. Reads can pass buffered writes, but the processor is self-consistent.

3. Writes to memory are always carried out in program order, with the exception of writes

executed with the CLFLUSH instruction and streaming stores (writes) executed with the

non-temporal move instructions (MOVNTI, MOVNTQ, MOVNTDQ, MOVNTPS, and

MOVNTPD).

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