Intel B940 Datasheet download pdf (Page 258)

Processor Configuration Registers

258 Datasheet, Volume 2

23 RO 0b

Isochrony (ISOCH)

0 = Indicates this DMA-remapping hardware unit has no critical isochronous

requesters in its scope.

1 = Indicates this DMA-remapping hardware unit has one or more critical

isochronous requesters in its scope. To ensure isochronous performance,

software must ensure invalidation operations do not impact active DMA

streams from such requesters. This implies that when DMA is active,

software perform page-selective invalidations (instead of coarser

invalidations).

22 RO 0b

Zero Length Read (ZLR)

0 = Indicates the remapping hardware unit blocks (and treats as fault) zero

length DMA read requests to write-only pages.

1 = Indicates the remapping hardware unit supports zero length DMA read

requests to write-only pages.

21:16 RO 23h

Maximum Guest Address Width (MGAW)

This field indicates the maximum DMA virtual addressability supported by

remapping hardware.

The Maximum Guest Address Width (MGAW) is computed as (N+1), where N

is the value reported in this field. For example, a hardware implementation

supporting 48-bit MGAW reports a value of 47 (101111b) in this field.

If the value in this field is X, untranslated and translated DMA requests to

addresses above 2^^(x+1) – 1 are always blocked by hardware. Translation

requests to address above 2^^(X+1) – 1 from allowed devices return a null

Translation Completion Data Entry with R=W=0.

Guest addressability for a given DMA request is limited to the minimum of

the value reported through this field and the adjusted guest address width of

the corresponding page-table structure. (Adjusted guest address widths

supported by hardware are reported through the SAGAW field).

15:13 RO 000b Reserved

12:8 RO 02h

Supported adjusted guest address width (SAGAW)

This 5-bit field indicates the supported adjusted guest address widths (which

in turn represents the levels of page-table walks for the 4KB base page size)

supported by the hardware implementation.

A value of 1 in any of these bits indicates the corresponding adjusted guest

address width is supported. The adjusted guest address widths

corresponding to various bit positions within this field are:

0h = 30-bit AGAW (2-level page-table)

1h = 39-bit AGAW (3-level page-table)

2h = 48-bit AGAW (4-level page-table)

3h = 57-bit AGAW (5-level page-table)

4h = 64-bit AGAW (6-level page-table)

Software must ensure that the adjusted guest address width used to set up

the page tables is one of the supported guest address widths reported in this

field.

7RO 0b

Caching Mode (CM)

0 = Not-present and erroneous entries are not cached in any of the

remapping caches. Invalidations are not required for modifications to

individual not present or invalid entries. However, any modifications that

result in decreasing the effective permissions or partial permission

increases require invalidations for them to be effective.

1 = Not-present and erroneous mappings may be cached in the remapping

caches. Any software updates to the remapping structures (including

updates to “notpresent” or erroneous entries) require explicit

invalidation.

Hardware implementations of this architecture must support a value of 0 in

this field. Refer to the VTd specification for more details on Caching Mode.

B/D/F/Type: 0/2/0/GFXVTBAR

Address Offset: 8–Fh

Reset Value: 00C0000020230272h

Access: RO

Bit Attr

Reset

Value

Description

1 2 ... 253 254 255 256 257 258 259 260 261 262 263 ... 359 360

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Intel B940 Datasheet Page 258

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