Introduction
14 Datasheet, Volume 2
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Datasheet – Volume 2
1
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Legal Lines and Disclaimers
2
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Contents
3
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4 Datasheet, Volume 2
4
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Datasheet, Volume 2 5
5
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6 Datasheet, Volume 2
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Datasheet, Volume 2 7
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8 Datasheet, Volume 2
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Datasheet, Volume 2 9
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10 Datasheet, Volume 2
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Datasheet, Volume 2 11
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Revision History
12
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1 Introduction
13
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Introduction
14
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2 Processor Configuration
15
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2.2 System Address Map
17
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18 Datasheet, Volume 2
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2.2.1 Legacy Address Range
19
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Datasheet, Volume 2 21
21
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2.2.2.2 TSEG
22
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2.2.2.5 Pre-allocated Memory
23
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2.2.2.7 Intel
24
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Management Engine (Intel
24
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ME) UMA
24
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Datasheet, Volume 2 25
25
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2.2.2.10 High BIOS Area
26
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Datasheet, Volume 2 27
27
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2.2.3.1 Programming Model
28
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HOST/SYSTEM VIEW
29
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PHYSICAL MEMORY
29
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(DRAM CONTROLLER VIEW)
29
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Datasheet, Volume 2 33
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34 Datasheet, Volume 2
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2.2.9 I/O Address Space
35
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36 Datasheet, Volume 2
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Datasheet, Volume 2 37
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2.4 Configuration Mechanisms
38
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Datasheet, Volume 2 39
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40 Datasheet, Volume 2
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Datasheet, Volume 2 41
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42 Datasheet, Volume 2
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Datasheet, Volume 2 43
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2.6 I/O Mapped Registers
44
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2.7.6 CC—Class Code Register
49
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TXT Lockable
54
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1:0 to 11b
56
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4) from
58
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B0h, bits 15:4)
58
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2.8 MCHBAR Registers
66
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00h RW
67
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Register Symbol Register Name
67
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208–209h
73
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20A–20Bh
74
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24D–24Fh
74
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250-251h
75
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252–255h
76
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256–257h
77
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258–25Ah
77
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269–26Eh
79
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298–29Bh
82
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29C–29Fh
84
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2B4–2B7h
84
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600–601h
86
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602–603h
86
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604–605h
86
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64D–64Fh
88
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650–651h
88
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652–655h
89
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656–657h
90
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658–65Ah
90
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660–663h
91
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6B4–6B7h
93
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C20–C27h
94
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1001–1002h
94
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1004–1005h
95
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101E–101Fh
100
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Register
107
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10EC–10EDh
108
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2C20–2C22h
109
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2.9 EPBAR Registers
110
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2.10 PCI Device 1 Registers
115
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PCI device
117
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Port Command Register
140
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11:10 RW-O 11b
143
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OS's during run time
155
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104–107h
156
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108–10Bh
157
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10C–10Dh
157
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110–113h
158
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23 RO 0b Reserved
158
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114–117h
158
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11A–11Bh
159
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2.12 DMIBAR Registers
161
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Declaration Capability
169
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2.13.6 CC—Class Code Register
177
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Range Address Register
179
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GMADR register
180
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2.14 Device 2 I/O Registers
183
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100–107h
211
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108–10Fh
212
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200–20Fh
214
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F00–F03h
215
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F04–F07h
216
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Dedication
217
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F08–F0Bh
218
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FFC–FFFh
219
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2.16 DMI VC1 REMAP Registers
221
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2.17.2 GFXPLL1—GFX PLL BIOS
254
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2.18 GFXVTBAR Registers
255
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Address Register
281
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2.19 PCI Device 6 Registers
288
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2.19.45 RSTS—Root Status
327
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2.21 Intel
332
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Specific Registers
332
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110–117h
333
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330–337h
333
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Lower Half Register
334
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Upper Half Register
334
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QuickPath Architecture
335
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System Address Decode
335
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Register Description
335
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QPI Link 0 Registers
340
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QPI Physical 0 Registers
341
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3.4 PCI Standard Registers
342
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3.4.4 CCR—Class Code Register
344
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Identification Register
345
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3.4.7 PCICMD—Command Register
346
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3.5.1 MAX_RTIDS
349
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3.6.1 SAD_PAM0123
349
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3.6.2 SAD_PAM456
351
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3.6.3 SAD_HEN
352
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3.6.4 SAD_SMRAM
353
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3.6.5 SAD_PCIEXBAR
354
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3.7 Intel
356
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QPI Link Registers
356
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3.8 Intel
357
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QPI Physical Layer Registers
357
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360 Datasheet, Volume 2
360
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