Datasheet, Volume 2 183
Processor Configuration Registers
2.13.17 MINGNT—Minimum Grant Register
2.13.18 MAXLAT—Maximum Latency Register
2.14 Device 2 I/O Registers
B/D/F/Type: 0/2/0/PCI
Address Offset: 3Eh
Reset Value: 00h
Access: RO
Bit Attr
Reset
Value
Description
7:0 RO 00h
Minimum Grant Value (MGV)
The IGD does not burst as a PCI compliant master.
B/D/F/Type: 0/2/0/PCI
Address Offset: 3Fh
Reset Value: 00h
Access: RO
Bit Attr
Reset
Value
Description
7:0 RO 00h
Maximum Latency Value (MLV)
The IGD has no specific requirements for how often it needs to access the
PCI bus.
Address
Offset
Register
Symbol
Register Name Reset Value Access
0–3h Index MMIO Address Register 0000_0000h RW
4–7h Data MMIO Data Register 0000_0000h RW
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