Intel B940 Datasheet download pdf (Page 355)

Datasheet, Volume 2 355

Intel

QuickPath Architecture System Address Decode Register Description

3.6.6 SAD_DRAM_RULE_0, SAD_DRAM_RULE_1,

SAD_DRAM_RULE_2, SAD_DRAM_RULE_3,

SAD_DRAM_RULE_4, SAD_DRAM_RULE_5,

SAD_DRAM_RULE_6, SAD_DRAM_RULE_7

This register provides the SAD DRAM rules. Address Map for package determination.

Device: 0

Function: 1

Offset: 80h, 84h, 88h, 8Ch, 90h, 94h, 98h, 9Ch

Access as a Dword

Bit Type

Reset

Value

Description

31:20 RV 0 Reserved

19:6 RW –

LIMIT

DRAM rule top limit address. Must be strictly greater than previous rule,

even if this rule is disabled, unless this rule and all following rules are

disabled. Lower limit is the previous rule (or 0 if it is first rule). This field is

compared against MA[39:26] in the memory address map.

5:3 RV 0 Reserved

2:1 RW –

MODE

DRAM rule interleave mode. If a DRAM_RULE hits a 3 bit number is used to

index into the corresponding interleave_list to determine which package

the DRAM belongs to. This mode selects how that number is computed.

00 = Address bits {8,7,6}.

01 = Address bits {8,7,6} XORed with {18,17,16}.

10 = Address bit {6}, MOD3(Address[39..6]). (Note 6 is the high order

bit)

11 = Reserved.

0RW 0

ENABLE

Enable for DRAM rule. If Enabled Range between this rule and previous

rule is Directed to HOME channel (unless overridden by other dedicated

address range registers). If disabled, all accesses in this range are directed

in MMIO to the IOH.

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Intel B940 Datasheet Page 355