Intel B940 Datasheet download pdf (Page 234)

Processor Configuration Registers

234 Datasheet, Volume 2

2.16.8 FSTS_REG—Fault Status Register

This register indicates the various error status.

B/D/F/Type: 0/0/0/DMIVC1REMAP

Address Offset: 34–37h

Reset Value: 00000000h

Access: RW1C-S, RO-V-S, RO

Bit Attr

Reset

Value

Description

31:16 RO 0000h Reserved

15:8 RO-V-S 00h

Fault Record Index (FRI)

This field is valid only when the PPF field is set.

The FRI field indicates the index (from base) of the fault recording register to

which the first pending fault was recorded when the PPF field was set by

hardware.

The value read from this field is undefined when the PPF field is clear.

7RO 0bReserved

RW1C-

Invalidation Time-out Error (ITE)

Hardware detected a Device-IOTLB invalidation completion time-out. At this

time, a fault event may be generated based on the programming of the Fault

Event Control register.

Hardware implementations not supporting Device-IOTLBs implement this bit as

reserved.

RW1C-

Invalidation Completion Error (ICE)

Hardware received an unexpected or invalid Device-IOTLB invalidation

completion. This could be due to either an invalid ITag or invalid source-id in an

invalidation completion response. At this time, a fault event may be generated

based on the programming of the Fault Event Control register.

Hardware implementations not supporting Device-IOTLBs implement this bit as

reserved.

4RO 0b

Invalidation Queue Error (IQE)

Hardware detected an error associated with the invalidation queue. This could

be due to either a hardware error while fetching a descriptor from the

invalidation queue, or hardware detecting an erroneous or invalid descriptor in

the invalidation queue. At this time, a fault event may be generated based on

the programming of the Fault Event Control register.

Hardware implementations not supporting queued invalidations implement this

bit as reserved.

RW1C-

Advanced Pending Fault (APF)

When this field is Clear, hardware sets this field when the first fault record (at

index 0) is written to a fault log. At this time, a fault event is generated based

on the programming of the Fault Event Control register.

Software writing 1 to this field clears it. Hardware implementations not

supporting advanced fault logging implement this bit as reserved.

RW1C-

Advanced Fault Overflow (AFO)

Hardware sets this field to indicate advanced fault log overflow condition. At

this time, a fault event is generated based on the programming of the Fault

Event Control register.

Software writing 1 to this field clears it. Hardware implementations not

supporting advanced fault logging implement this bit as reserved.

1RO-V-S 0b

Primary Pending Fault (PPF)

This field indicates if there are one or more pending faults logged in the fault

recording registers. Hardware computes this field as the logical OR of Fault (F)

fields across all the fault recording registers of this DMA-remapping HW unit.

0 = No pending faults in any of the fault recording registers.

1 = One or more fault recording registers has pending faults.

The FRI field is updated by hardware whenever the PPF field is set by

hardware. Also, depending on the programming of Fault Event Control register,

a fault event is generated when hardware sets this field.

RW1C-

imary Fault Overflow (PFO)

Hardware sets this field to indicate overflow of fault recording registers.

Software writing 1 clears this field. When this field is set, hardware does not

record any new faults until software clears this field.

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Intel B940 Datasheet Page 234

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