Intel B940 Datasheet download pdf (Page 118)

Processor Configuration Registers

118 Datasheet, Volume 2

8RW 0b

SERR# Message Enable (SERRE1)

This bit controls Device 1 SERR# messaging. The processor communicates

the SERR# condition by sending an SERR message to the PCH. This bit, when

set, enables reporting of non-fatal and fatal errors detected by the device to

the Root Complex. Note that errors are reported if enabled either through

this bit or through the PCI-Express specific bits in the Device Control

In addition, for Type 1 configuration space header devices, this bit, when set,

enables transmission by the primary interface of ERR_NONFATAL and

ERR_FATAL error messages forwarded from the secondary interface. This bit

does not affect the transmission of forwarded ERR_COR messages.

0 = The SERR message is generated by the processor for Device 1 only

under conditions enabled individually through the Device Control

1 = The processor is enabled to generate SERR messages which will be sent

to the PCH for specific Device 1 error conditions generated/detected on

the primary side of the virtual PCI to PCI bridge (not those received by

the secondary side). The status of SERRs generated is reported in the

PCISTS1 register.

7RO 0b

Reserved

Not Applicable or Implemented. Hardwired to 0.

6RW 0b

Parity Error Response Enable (PERRE)

Controls whether or not the Master Data Parity Error bit in the PCI Status

0 = Master Data Parity Error bit in PCI Status register can NOT be set.

1 = Master Data Parity Error bit in PCI Status register CAN be set.

5RO 0b

VGA Palette Snoop (VGAPS)

Not Applicable or Implemented. Hardwired to 0.

4RO 0b

Memory Write and Invalidate Enable (MWIE)

Not Applicable or Implemented. Hardwired to 0.

3RO 0b

Special Cycle Enable (SCE)

Not Applicable or Implemented. Hardwired to 0.

2RW 0b

Bus Master Enable (BME)

This bit controls the ability of the PEG port to forward Memory and IO

Read/Write Requests in the upstream direction.

0 = This device is prevented from making memory or IO requests to its

primary bus. Note that according to PCI Specification, as MSI interrupt

messages are in-band memory writes, disabling the bus master enable

bit prevents this device from generating MSI interrupt messages or

passing them from its secondary bus to its primary bus. Upstream

memory writes/reads, IO writes/reads, peer writes/reads, and MSIs will

all be treated as illegal cycles. Writes are forwarded to memory address

C0000h with byte enables de-asserted. Reads will be forwarded to

memory address C0000h and will return Unsupported Request status (or

Master abort) in its completion packet.

1 = This device is allowed to issue requests to its primary bus. Completions

for previously issued memory read requests on the primary bus will be

issued when the data is available. This bit does not affect forwarding of

Completions from the primary interface to the secondary interface.

1RW 0b

Memory Access Enable (MAE)

0 = All of device 1's memory space is disabled.

1 = Enable the Memory and Pre-fetchable memory address ranges defined

in the MBASE1, MLIMIT1, PMBASE1, and PMLIMIT1 registers.

0RW 0b

IO Access Enable (IOAE)

0 = All of device 1's I/O space is disabled.

1 = Enable the I/O address range defined in the IOBASE1, and IOLIMIT1

registers.

B/D/F/Type: 0/1/0/PCI

Address Offset: 4–5h

Reset Value: 0000h

Access: RO, RW

Bit Attr

Reset

Value

Description

1 2 ... 113 114 115 116 117 118 119 120 121 122 123 ... 359 360

Comments to this Manuals

No comments

Intel B940 Datasheet Page 118

Comments to this Manuals

Related products and manuals for Processors Intel B940