Intel B940 Datasheet download pdf (Page 219)

Datasheet, Volume 2 219

Processor Configuration Registers

2.15.34 VTPOLICY—DMA Remap Engine Policy Control

This registers contains all the policy bits related to the DMA remap engine.

B/D/F/Type: 0/0/0/VC0PREMAP

Address Offset: FFC–FFFh

Reset Value: 00000000h

Access: RW-L

Bit Attr

Reset

Value

Description

31 RW-L 0b

DMA Remap Engine Policy Lock-Down (DMAR_LCKDN)

This register bit protects all the DMA remap engine specific policy

configuration registers. Once this bit is set by software all the DMA remap

engine registers within the range F00h to FFCh will be read-only. This bit can

only be clear through platform reset.

30 RW-L 0b

DMA Remap Engine Policy Control (DMAR_CTL)

lt_gv_vt_scr_reserved_fault_en.

0 = "Default" Hardware support's reserved field programming faults in root,

context and page translation structure (that is, fault code of Ah, Bh, Ch).

1 = Hardware ignores reserved field programming faults in the root, context

and page translation structure.

29:23 RW-L 00h Reserved

22 RW-L 0b

Lookup Policy TLB Invalidation (LKUPPOLTLBINVL)

VC0/VCp Remap Engine TLB Lookup Policy On TLB Invalidation.

1 = Mask all TLB Lookup to VC0/VCp remap engine during TLB Invalidation

Window.

0 = Continue to perform TLB lookup to VC0/VCp remap engine during TLB

Invalidation Window.

TLB Invalidation Window refers to the period from when the TLB Invalidation

is initiated until all the outstanding DMA read and write cycles at the point of

TLB Invalidation are initiated are Globally Ordered.

21 RW-L 0b

PEG1 VC0 Read Hit Queue Throttling (PEG1VC0RDHTQT)

1 = Throttle the outlet PEG0 VC1 Read Hit Queue to fill up the queue.

0 = No throttling at the outlet of the PEG1 VC0 Read Hit Queue.

20 RW-L 0b

PEG1 VC0 Write Queue Throttling (PEG1VC0WRHTQT)

1 = Throttle the outlet PEG1 VC0 Write Hit Queue to fill up the queue.

0 = No throttling at the outlet of the PEG1 VC0 Write Hit Queue.

19 RW-L 0b

PEG0 VC0 Read Hit Queue Throttling (PEGVC0RDHTQT)

1 = Throttle the outlet PEG0 VC0 Read Hit Queue to fill up the queue.

0 = No throttling at the outlet of the PEG0 VC0 Read Hit Queue.

18 RW-L 0b

PEG0 VC0 Write Queue Throttling (PEGVC0WRHTQT)

1 = Throttle the outlet PEG0 VC0 Write Hit Queue to fill up the queue.

0 = No throttling at the outlet of the PEG0 VC0 Write Hit Queue.

17 RW-L 0b

DMI VCp Hit Queue Throttling (DMIVCPHTQT)

1 = Throttle the outlet DMI VCp Hit Queue to fill up the queue.

0 = No throttling at the outlet of the DMI VCp Hit Queue.

16 RW-L 0b

DMI VC0 Read Hit Queue Throttling (DMIVC0RDHTQT)

1 = Throttle the outlet DMI VC0 Read Hit Queue to fill up the queue.

0 = No throttling at the outlet of the DMI VC0 Read Hit Queue.

15 RW-L 0b

DMI VC0 Write Queue Throttling (DMIVC0WRHTQT)

1 = Throttle the outlet DMI VC0 Write Hit Queue to fill up the queue.

0 = No throttling at the outlet of the DMI VC0 Write Hit Queue.

14 RW-L 0b

PEG1 Context Cache TLBR (PEG1CTXTTLBR)

This is a TLBR policy bit for PEG1VC0 Context Cache

13 RW-L 0b

PEG1 L1 TLBR (PEG1L1TLBR)

This is a TLBR policy bit for PEG1VC0 L1 Cache

1 2 ... 214 215 216 217 218 219 220 221 222 223 224 ... 359 360

Comments to this Manuals

No comments

Intel B940 Datasheet Page 219

Comments to this Manuals

Related products and manuals for Processors Intel B940