Intel B940 Datasheet download pdf (Page 4)

4 Datasheet, Volume 2

2.7.12 MCHBAR—MCH Memory Mapped Register Range Base Register..................52

2.7.13 GGC—Graphics Control Register ............................................................53

2.7.14 DEVEN—Device Enable Register.............................................................54

2.7.15 DMIBAR—Root Complex Register Range Base Address Register..................55

2.7.16 LAC—Legacy Access Control Register......................................................56

2.7.17 TOUUD—Top of Upper Usable DRAM Register ..........................................58

2.7.18 GBSM— Graphics Base of Pre-allocated Memory Register ..........................58

2.7.19 BGSM—Base of GTT Pre-allocated Memory Register.................................59

2.7.20 TSEGMB—TSEG Memory Base Register...................................................59

2.7.21 TOLUD—Top of Low Usable DRAM Register..............................................60

2.7.22 PBFC—Primary Buffer Flush Control Register ...........................................61

2.7.23 SBFC—Secondary Buffer Flush Control Register .......................................61

2.7.24 ERRSTS—Error Status Register..............................................................62

2.7.25 ERRCMD—Error Command Register........................................................63

2.7.26 SMICMD—SMI Command Register..........................................................64

2.7.27 SKPD—Scratchpad Data Register ...........................................................64

2.7.28 CAPID0—Capability Identifier Register....................................................65

2.7.29 MCSAMPML—Memory Configuration, System Address

Map and Pre-allocated Memory Lock Register ..........................................65

2.8 MCHBAR Registers.............................................................................................66

2.8.1 CSZMAP—Channel Size Mapping Register................................................68

2.8.2 CHDECMISC—Channel Decode Miscellaneous Register ..............................69

2.8.3 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 Register...................70

2.8.4 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 Register...................71

2.8.5 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 Register...................71

2.8.6 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 Register...................72

2.8.7 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute Register...........................73

2.8.8 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute Register...........................74

2.8.9 C0WRDATACTRL—Channel 0 Write Data Control Register ..........................74

2.8.10 C0CYCTRKPCHG—Channel 0 CYCTRK PCHG Register.................................75

2.8.11 C0CYCTRKACT—Channel 0 CYCTRK ACT Register .....................................76

2.8.12 C0CYCTRKWR—Channel 0 CYCTRK WR Register.......................................77

2.8.13 C0CYCTRKRD—Channel 0 CYCTRK READ Register ....................................77

2.8.14 C0CYCTRKREFR—Channel 0 CYCTRK REFR Register..................................78

2.8.15 C0PWLRCTRL—Channel 0 Partial Write Line Read Control Register..............78

2.8.16 C0REFRCTRL—Channel 0 DRAM Refresh Control Register ..........................79

2.8.17 C0JEDEC—Channel 0 JEDEC Control Register...........................................81

2.8.18 C0ODT—Channel 0 ODT Matrix Register..................................................82

2.8.19 C0ODTCTRL—Channel 0 ODT Control Register .........................................84

2.8.20 C0DTC—Channel 0 DRAM Throttling Control Register................................84

2.8.21 C0RSTCTL—Channel 0 Reset Controls Register ........................................85

2.8.22 C1DRB0—Channel 1 DRAM Rank Boundary Address 0 Register...................86

2.8.23 C1DRB1—Channel 1 DRAM Rank Boundary Address 1 Register...................86

2.8.24 C1DRB2—Channel 1 DRAM Rank Boundary Address 2 Register...................86

2.8.25 C1DRB3—Channel 1 DRAM Rank Boundary Address 3 Register...................87

2.8.26 C1DRA01—Channel 1 DRAM Rank 0,1 Attributes Register..........................87

2.8.27 C1DRA23—Channel 1 DRAM Rank 2, 3 Attributes Register.........................87

2.8.28 C1WRDATACTRL—Channel 1 Write Data Control Register..........................88

2.8.29 C1CYCTRKPCHG—Channel 1 CYCTRK PCHG Register.................................88

2.8.30 C1CYCTRKACT—Channel 1 CYCTRK ACT Register .....................................89

2.8.31 C1CYCTRKWR—Channel 1 CYCTRK WR Register.......................................90

2.8.32 C1CYCTRKRD—Channel 1 CYCTRK READ Register ....................................90

2.8.33 C1CKECTRL—Channel 1 CKE Control Register..........................................91

2.8.34 C1PWLRCTRL—Channel 1 Partial Write Line Read Control Register..............92

2.8.35 C1ODTCTRL—Channel 1 ODT Control Register .........................................92

2.8.36 C1DTC—Channel 1 DRAM Throttling Control Register................................93

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Intel B940 Datasheet Page 4

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