Intel B940 Datasheet download pdf (Page 26)

Processor Configuration Registers

26 Datasheet, Volume 2

2.2.2.9 APIC Configuration Space (FEC0_0000h–FECF_FFFFh)

This range is reserved for APIC configuration space. The I/O APIC(s) usually reside in

the PCH portion of the chipset, but may also exist as stand-alone components like PXH.

The IOAPIC spaces are used to communicate with IOAPIC interrupt controllers that

may be populated in the system. Since it is difficult to relocate an interrupt controller

using plug-and-play software, fixed address decode regions have been allocated for

them. Processor accesses to the default IOAPIC region (FEC0_0000h to FEC7_FFFFh)

are always forwarded to DMI.

The processor optionally supports additional I/O APICs behind the PCI Express

“Graphics” port. When enabled using the PCI Express Configuration register (Device 1,

Offset 200h and Device 6, Offset 200h), the PCI Express port(s) will positively decode a

subset of the APIC configuration space. Specifically,

• Device 6 can be enabled to claim FEC8_0000h thru FECB_FFFFh.

• Device 1 can be enabled to claim FECC_0000h thru FECF_FFFFh.

Memory requests to this range would then be forwarded to the PCI Express port. This

mode is intended for the entry Workstation SKU of the processor, and would be

disabled in typical Desktop systems. When disabled, any access within entire APIC

Configuration space (FEC0_0000h to FECF_FFFFh) is forwarded to DMI.

2.2.2.9.1 MSI Interrupt Memory Space (FEE0_0000 – FEEF_FFFF)

Any PCI Express or DMI device may issue a Memory Write to 0FEEx_xxxxh. This

Memory Write cycle does not go to DRAM. The processor will forward this Memory Write

along with the data to the processor as a QPI Interrupt Message Transaction.

This interrupt message will be delivered to the processor as an IntPhysical or IntLogical

message.

2.2.2.10 High BIOS Area

For security reasons, the processor will now positively decode this range to DMI. This

positive decode will ensure any overlapping ranges will be ignored.

The top 2 MB (FFE0_0000h – FFFF_FFFFh) of the PCI Memory Address Range is

reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20

alias of the system BIOS. The processor begins execution from the High BIOS after

reset. This region is positively decoded to DMI Interface so that the upper subset of this

region aliases to 16 MB – 256 KB range. The actual address space required for the

BIOS is less than 2 MB but the minimum processor MTRR range for this region is 2 MB

so that full 2 MB must be considered.

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Intel B940 Datasheet Page 26