Intel B940 Datasheet Page 15

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Datasheet, Volume 2 15
Processor Configuration Registers
2 Processor Configuration
Registers
2.1 Register Terminology
Table 2-1 shows the register-related terminology that is used in this chapter.
Table 2-1. Register Terminology (Sheet 1 of 2)
Item Description
RO Read Only bit(s). Writes to these bits have no effect. These are static values only.
RO-V
Read Only/Volatile bit(s). Writes to these bits have no effect. These are status bits only. The
value to be read may change based on internal events.
RO-V-S
Read Only/Volatile/Sticky bit(s). Writes to these bits have no effect. These are status bits
only. The value to be read may change based on internal events. Bits are not returned to their
Reset Values by “warm” reset, but is reset with a cold/complete reset (for PCI Express* related
bits a cold reset is “Power Good Reset” as defined in the PCI Express Base Specification).
AF
Atomic Flag bit(s). The first time the bit is read with an enabled byte, it returns the value 0, but
a side-effect of the read is that the value changes to 1. Any subsequent reads with enabled bytes
return a 1 until a 1 is written to the bit. When the bit is read, but the byte is not enabled, the
state of the bit does not change, and the value returned is irrelevant, but will match the state of
the bit.
When a 0 is written to the bit, there is no effect. When a 1 is written to the bit, its value becomes
0, until the next byte-enabled read. When the bit is written, but the byte is not enabled, there is
no effect.
Conceptually, this is “Read to Set, Write 1 to Clear”
RW
Read/Write bit(s). These bits can be read and written by software. Hardware may only change
the state of this bit by reset.
RW1C
Read/Write 1 to Clear bit(s). These bits can be read. Internal events may set this bit. A
software write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect.
RW1C-L-S
Read/Write 1 to Clear/Lockable/Sticky bit(s). These bits can be read. Internal events may
set this bit. A software write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has
no effect. Bits are not cleared by “warm” reset, but is reset with a cold/complete reset (for PCI
Express related bits a cold reset is “Power Good Reset” as defined in the PCI Express Base spec).
Additionally there is a Key bit (which is marked RW-K or RW-L-K) that, when set, prohibits this bit
field from being writable (bit field becomes Read Only/Volatile).
RW1C-S
Read/Write 1 to Clear/Sticky bit(s). These bits can be read. Internal events may set this bit.
A software write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect.
Bits are not cleared by "warm" reset, but is reset with a cold/complete reset (for PCI Express
related bits a cold reset is “Power Good Reset” as defined in the PCI Express Base spec).
RW-K
Read/Write/Key bit(s). These bits can be read and written by software. Additionally this bit,
when set, prohibits some other target bit field from being writable (bit fields become Read Only).
RW-L
Read/Write/Lockable bit(s). These bits can be read and written by software. Additionally
there is a Key bit (which is marked RW-K or RW-L-K) that, when set, prohibits this bit field from
being writable (bit field becomes Read Only).
RW-L-K
Read/Write/Lockable/Key bit(s). These bits can be read and written by software. This bit,
when set, prohibits some other bit field(s) from being writable (bit fields become Read Only).
Additionally there is a Key bit (which is marked RW-K or RW-L-K) that, when set, prohibits this bit
field from being writable (bit field becomes Read Only).
Conceptually, this may be a cascaded lock, or it may be self-locking when in its non-default state.
When self-locking, it differs from RW-O in that writing back the Reset Value will not set the lock.
RW-V
Write/Volatile bit(s). These bits can be read and written by software. Hardware may set or
clear the bit based on internal events, possibly sooner than any subsequent software read could
retrieve the value written.
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