Intel B940 Datasheet download pdf (Page 335)

Datasheet, Volume 2 335

Intel

QuickPath Architecture System Address Decode Register Description

3 Intel

QuickPath Architecture

System Address Decode

The processor supports PCI configuration space accesses using the mechanism denoted

as Configuration Mechanism in the PCI specification as defined in the PCI Local Bus

Specification, Revision 2.3, as well as the PCI Express* enhanced configuration

mechanism as specified in the PCI Express Base Specification, Revision 1.1. All the

registers are organized by bus, device, function, etc. as defined in the PCI Express Base

Specification, Revision 1.1. All processor registers appear on the PCI bus assigned for

the processor socket. Bus number is derived by the maximum bus range setting and

processor socket number. All multi-byte numeric fields use “little-endian” ordering (that

is, lower addresses contain the least significant parts of the field).

As processor features vary by SKU, not all of the register descriptions in this chapter

apply to all processors. This document highlights registers that do not apply to all

processor SKUs. Refer to the particular processor specification update for a list of

features supported.

3.1 Register Terminology

Registers and register bits are assigned one or more of the following attributes. These

attributes define the behavior of register and the bit(s) that are contained within. All

bits are set to Reset Values by a hard reset. Sticky bits retain their states between hard

resets.

Table 3-1. Register Terminology (Sheet 1 of 2)

Term Description

Read Only. If a register bit is read only, the hardware sets its state. The bit may be read by

software. Writes to this bit have no effect.

Write Only. The register bit is not implemented as a bit. The write causes some hardware

event to take place.

RW Read/Write. A register bit with this attribute can be read and written by software.

Read Clear: The bit or bits can be read by software, but the act of reading causes the value to

be cleared.

RCW

Read Clear/Write: A register bit with this attribute will get cleared after the read. The register

bit can be written.

RW1C

Read/Write 1 Clear. A register bit with this attribute can be read or cleared by software. In

order to clear this bit, a one must be written to it. Writing a zero will have no effect.

RW0C

Read/Write 0 Clear. A register bit with this attribute can be read or cleared by software. In

order to clear this bit, a zero must be written to it. Writing a one will have no effect.

RW1S

Read/Write 1 Set: A register bit can be either read or set by software. In order to set this bit,

a one must be written to it. Writing a zero to this bit has no effect. Hardware will clear this bit.

RW0S

Read/Write 0 Set: A register bit can be either read or set by software. In order to set this bit,

a zero must be written to it. Writing a one to this bit has no effect. Hardware will clear this bit.

RWL

Read/Write/Lock. A register bit with this attribute can be read or written by software.

Hardware or a configuration bit can lock the bit and prevent it from being updated.

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