Intel B940 Datasheet download pdf (Page 146)

Processor Configuration Registers

146 Datasheet, Volume 2

2.10.41 LSTS—Link Status Register

This register indicates PCI Express link status.

B/D/F/Type: 0/1/0/PCI

Address Offset: B2–B3h

Reset Value: 1000h

Access: RW1C, RO

Bit Attr

Reset

Value

Description

15 RW1C 0b

Link Autonomous Bandwidth Status (LABWS)

This bit is set to 1b by hardware to indicate that hardware has autonomously

changed link speed or width, without the port transitioning through DL_Down

status, for reasons other than to attempt to correct unreliable link operation.

This bit must be set if the Physical Layer reports a speed or width change was

initiated by the downstream component that was indicated as an

autonomous change.

This bit must be set when the upstream component receives eight

consecutive TS1 or TS2 ordered sets with the Autonomous Change bit set.

14 RW1C 0b

Link Bandwidth Management Status (LBWMS)

This bit is set to 1b by hardware to indicate that either of the following has

occurred without the port transitioning through DL_Down status:

• A link retraining initiated by a write of 1b to the Retrain Link bit has

completed.

Note: This bit is Set following any write of 1b to the Retrain Link bit, including

when the Link is in the process of retraining for some other reason.

• Hardware has autonomously changed link speed or width to attempt to

correct unreliable link operation, either through an LTSSM time-out or a

higher level process.

This bit must be set if the Physical Layer reports a speed or width change was

initiated by the downstream component that was not indicated as an

autonomous change.

13 RO 0b

Data Link Layer Link Active (Optional) (DLLLA)

This bit indicates the status of the Data Link Control and Management State

Machine. It returns a 1b to indicate the DL_Active state, 0b otherwise.

This bit must be implemented if the corresponding Data Link Layer Active

Capability bit is implemented. Otherwise, this bit must be hardwired to 0b.

12 RO 1b

Slot Clock Configuration (SCC)

0 = The device uses an independent clock irrespective of the presence of a

reference on the connector.

1 = The device uses the same physical reference clock that the platform

provides on the connector.

11 RO 0b

Link Training (LTRN)

This bit indicates that the Physical Layer LTSSM is in the Configuration or

Recovery state, or that 1b was written to the Retrain Link bit but Link training

has not yet begun. Hardware clears this bit when the LTSSM exits the

Configuration/Recovery state once Link training is complete.

10 RO 0b

Undefined (Undefined)

The value read from this bit is undefined. In previous versions of this

specification, this bit was used to indicate a Link Training Error. System

software must ignore the value read from this bit. System software is

permitted to write any value to this bit.

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Intel B940 Datasheet Page 146

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