Intel B940 Datasheet download pdf (Page 211)

Datasheet, Volume 2 211

Processor Configuration Registers

2.15.28 IVA_REG—Invalidate Address Register

This register provides the DMA address whose corresponding IOTLB entry needs to be

invalidated through the corresponding IOTLB Invalidate register. This register is a

write-only register. Value returned on reads of this register is undefined. There is an

IVA_REG for each IOTLB Invalidation unit supported by hardware.

B/D/F/Type: 0/0/0/VC0PREMAP

Address Offset: 100–107h

Reset Value: 0000000000000000h

Access: W, RO

Bit Attr

Reset

Value

Description

63:12 W

00000000

00000h

Address (Addr)

Software provides the DMA address that needs to be page-selectively

invalidated. To request a page-selective invalidation request to hardware,

software must first write the appropriate fields in this register, and then issue

appropriate page-selective invalidate command through the IOTLB_REG.

Hardware ignores bits 63:N, where N is the maximum guest address width

(MGAW) supported. Value returned on read of this field is undefined.

11:7 RO 00h Reserved

6W 0h

Invalidation Hint (IH)

The field provides hint to hardware to preserve or flush the non-leaf (page-

directory) entries that may be cached in hardware.

0 = Software may have modified both leaf and non-leaf page-table entries

corresponding to mappings specified in the ADDR and AM fields. On a

page selective invalidation request, hardware must flush both the

cached leaf and non-leaf page-table Value returned on a read of this

field is undefined. Entries corresponding to mappings specified by ADDR

and AM fields.

1 = Software has not modified any non-leaf page-table entries

corresponding to mappings specified in the ADDR and AM fields. On a

page-selective invalidation request, hardware may preserve the cached

non-leaf page-table entries corresponding to mappings specified by

ADDR and AM fields.

5:0 W 00h

Address Mask (AM)

The value in this field specifies the number of low order bits of the ADDR field

that must be masked for the invalidation operation. The Mask field enables

software to request invalidation of contiguous mappings for size-aligned

regions. For example: Mask Value ADDR bits masked Pages invalidated

Mask Value Addr bits masked Pg inval

0Nil 1

112 2

2 13:12 4

3 14:12 8

4 15:12 16

5 16:12 32

6 17:12 64

7 18:12 128

8 19:12 256

Hardware implementations report the maximum supported mask value

through the Capability register. Value returned on read of this field is

undefined.

1 2 ... 206 207 208 209 210 211 212 213 214 215 216 ... 359 360

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Intel B940 Datasheet Page 211

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