Processor Configuration Registers
90 Datasheet, Volume 2
2.8.31 C1CYCTRKWR—Channel 1 CYCTRK WR Register
This register provides Channel 1 CYCTRK WR control.
2.8.32 C1CYCTRKRD—Channel 1 CYCTRK READ Register
This register is for Channel 1 CYCTRK READ control.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 656–657h
Reset Value: 0000h
Access: RW
Bit Attr
Reset
Value
Description
15:12 RW 0h
ACT To Write Delay (C1sd_cr_act_wr)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the ACT and WRITE commands to the same rank-bank. This field corresponds
to tRCD_wr in the DDR specification.
11:8 RW 0h
Same Rank Write To Write Delayed (C1sd_cr_wrsr_wr)
This field indicates the minimum allowed spacing (in DRAM clocks) between
two WRITE commands to the same rank.
7:4 RW 0h
Different Rank Write to Write Delay (C1sd_cr_wrdr_wr)
This field indicates the minimum allowed spacing (in DRAM clocks) between
two WRITE commands to different ranks. This field corresponds to tWR_WR
in the DDR specification.
3:0 RW 0h
READ To WRTE Delay (C1sd_cr_rd_wr)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the READ and WRITE commands. This field corresponds to tRD_WR.
B/D/F/Type: 0/0/0/MCHBAR
Address Offset: 658–65Ah
Reset Value: 000000h
Access: RW, RO
Bit Attr
Reset
Value
Description
23:21 RO 0h Reserved
20:17 RW 0h
Min ACT To READ Delayed (C1sd_cr_act_rd)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the ACT and READ commands to the same rank-bank. This field corresponds
to tRCD_rd in the DDR specification.
16:12 RW 00000b
Same Rank Write To READ Delayed (C1sd_cr_wrsr_rd)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to the same rank.
This field corresponds to tWTR in the DDR specification.
11:8 RW 0000b
Different Ranks Write To READ Delayed (C1sd_cr_wrdr_rd)
This field indicates the minimum allowed spacing (in DRAM clocks) between
the WRITE and READ commands to different ranks.
This field corresponds to tWR_RD in the DDR specification.
7:4 RW 0000b
Same Rank Read To Read Delayed (C1sd_cr_rdsr_rd)
This field indicates the minimum allowed spacing (in DRAM clocks) between
two READ commands to the same rank.
3:0 RW 0000b
Different Ranks Read To Read Delayed (C1sd_cr_rddr_rd)
This field indicates the minimum allowed spacing (in DRAM clocks) between
two READ commands to different ranks. This field corresponds to tRD_RD.
Comments to this Manuals