Intel B940 Datasheet download pdf (Page 17)

Datasheet, Volume 2 17

Processor Configuration Registers

2.2 System Address Map

Note: The processor’s Multi Chip Package (MCP) conceptually consists of the processor and

the north bridge chipset (GMCH) combined together in a single package. Hence, this

section will have references to the processor as well as GMCH (or MCH) address

mapping.

The MCP supports 64 GB (36 bit) of addressable memory space and 64 KB+3 of

addressable I/O space. With the new QPI interface, the processor performs decoding

that historically occurred within the GMCH. Specifically, the GMCH address decoding for

processor initiated PAM, 15 MB–16 MB ISA hole, SMM CSEG/TSEG, PCIexBAR, and

DRAM accesses will occur within the processor and the GMCH has no direct knowledge.

In addition, the ME (device 3) will move to the PCH, so ME associated register ranges

have been removed from the graphics controller. This section focuses on how the

memory space is partitioned and what the separate memory regions are used for. I/O

address space has simpler mapping and is explained near the end of this section.

The MCP supports PEG port upper prefetchable base/limit registers. This allows the PEG

unit to claim IO accesses above 36 bit, complying with the PCI Express Base

Specificaiton 2.1. Addressing of greater than 4 GB is allowed on either the DMI

Interface or PCI Express interface. The MCP supports a maximum of 16 GB of DRAM.

No DRAM memory will be accessible above 16 GB. DRAM capacity is limited by the

number of address pins available.

When running in internal graphics mode, Tilex/Tiley/linear reads/writes to GMADR

range are supported. Write accesses to GMADR linear regions are supported from both

DMI and PEG. GMADR write accesses to tileX and tileY regions (defined using fence

registers) are not supported from DMI or the PEG port. GMADR read accesses are not

supported from either DMI or PEG.

In the following sections, it is assumed that all of the compatibility memory ranges

reside on the DMI Interface. The exception to this rule is VGA ranges, which may be

mapped to PCI Express*, or DMI, or to the internal graphics device (IGD). In the

absence of more specific references, cycle descriptions referencing PCI should be

interpreted as the DMI Interface/PCI, while cycle descriptions referencing PCI Express

or IGD are related to the PCI Express bus or the internal graphics device respectively.

The processor does not remap APIC or any other memory spaces above TOLUD (Top of

Low Usable DRAM). The TOLUD register is set to the appropriate value by BIOS. The

remapbase/remaplimit registers remap logical accesses bound for addresses above

4 GB onto physical addresses that fall within DRAM.

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Intel B940 Datasheet Page 17