Intel B940 Datasheet download pdf (Page 23)

Datasheet, Volume 2 23

Processor Configuration Registers

Once the protected low/high memory region registers are configured, bus master

protection to these regions is enabled through the Protected Memory Enable register.

For platforms with multiple DMA-remapping hardware units, each of the DMA-

remapping hardware units must be configured with the same protected memory

regions and enabled.

2.2.2.4 DRAM Protected Range (DPR)

This protection range only applies to DMA accesses and GMADR translations. It serves a

purpose of providing a memory range that is only accessible to processor streams.

The DPR range works independent of any other range, including the PMRC checks in

VTd. It occurs post any VTd translation. Therefore, incoming cycles are checked against

this range after the VTd translation and faulted if they hit this protected range, even if

they passed the VTd translation.

The system will set up:

1. 0 to (TSEG_BASE – DPR size – 1) for DMA traffic

2. TSEG_BASE to (TSEG_BASE – DPR size) as no DMA

After some time, software could request more space for not allowing DMA. It will get

some more pages and make sure there are no DMA cycles to the new region. DPR size

is changed to the new value. When it does this, there should not be any DMA cycles

going to DRAM to the new region.

If there were cycles from a rogue device to the new region, then those could use the

previous decode until the new decode can ensure PV. No flushing of cycles is required.

On a clock by clock basis proper decode with the previous or new decode needs to be

ensured.

All upstream cycles from 0 to (TSEG_BASE – 1 – DPR size), and not in the legacy holes

(VGA), are decoded to dram.

2.2.2.5 Pre-allocated Memory

Voids of physical addresses that are not accessible as general system memory and

reside within system memory address range (< TOLUD) are created for SMM-mode,

legacy VGA graphics compatibility, and graphics GTT stolen memory. It is the

responsibility of BIOS to properly initialize these regions.

2.2.2.6 Graphics Stolen Spaces

2.2.2.6.1 GTT Stolen Space (GSM)

GSM is allocated to store the GFX translation table entries, depending on VT-d support

it may be divided into 2 sections.

2.2.2.6.2 Global GTT Stolen Space (GGSM)

GGSM always exists regardless of VT-d as long as internal GFX is enabled. This space is

allocated to store accesses as page table entries are getting updated through virtual

GTTMMADR range. Hardware is responsible to map PTEs into this physical space.

Direct accesses to GGSM is not allowed, only hardware translations and fetches can be

directed to GGSM.

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Intel B940 Datasheet Page 23