Intel B940 Datasheet download pdf (Page 42)

Processor Configuration Registers

42 Datasheet, Volume 2

2.4.5 Bridge Related Configuration Accesses

Configuration accesses on PCI Express or DMI are PCI Express Configuration TLPs.

• Bus Number [7:0] is Header Byte 8 [7:0]

• Device Number [4:0] is Header Byte 9 [7:3]

• Function Number [2:0] is Header Byte 9 [2:0]

And special fields for this type of TLP:

• Extended Register Number [3:0] is Header Byte 10 [3:0]

• Register Number [5:0] is Header Byte 11 [7:2]

See the PCI Express Base Specification and the PCI Local Bus Specification Revision 3.0

for more information on both the PCI 3.0-compatible and PCI Express Enhanced

Configuration Mechanism and transaction rules.

2.4.5.1 PCI Express* Configuration Accesses

When the Bus Number of a type 1 Standard PCI Configuration cycle or PCI Express

Enhanced Configuration access matches the Device 1 Secondary Bus Number, a PCI

Express Type 0 Configuration TLP is generated on the PCI Express link targeting the

device directly on the opposite side of the link. This should be Device 0 on the bus

number assigned to the PCI Express link (likely Bus 1).

The device on other side of link must be Device 0. The processor will Master Abort any

Type 0 Configuration access to a non-zero device number. If there is to be more than

one device on that side of the link there must be a bridge implemented in the

downstream device.

When the bus number of a type 1 Standard PCI Configuration cycle or PCI Express

Enhanced Configuration access is within the claimed range (between the upper bound

of the bridge device’s Subordinate Bus Number register and the lower bound of the

bridge device’s Secondary Bus Number register) but does not match the Device 1

Secondary Bus Number, a PCI Express Type 1 Configuration TLP is generated on the

secondary side of the PCI Express link.

PCI Express Configuration Writes:

• Internally the processor will translate writes to PCI Express extended configuration

space to configuration writes on the backbone.

• Posted writes to extended space are non-posted on the PCI Express or DMI (that is,

translated to configuration writes)

1 2 ... 37 38 39 40 41 42 43 44 45 46 47 ... 359 360

No comments

Intel B940 Datasheet Page 42