Intel B940 Datasheet download pdf (Page 58)

Processor Configuration Registers

58 Datasheet, Volume 2

2.7.17 TOUUD—Top of Upper Usable DRAM Register

This 16 bit register defines the Top of Upper Usable DRAM.

Configuration software must set this value to TOM minus all EP pre-allocated memory if

reclaim is disabled. If reclaim is enabled, this value must be set to reclaim limit +

1byte, 64 MB aligned, since reclaim limit is 64 MB aligned. Address bits 19:0 are

assumed to be 000_0000h for the purposes of address comparison. The Host interface

positively decodes an address towards DRAM if the incoming address is less than the

value programmed in this register and greater than or equal to 4 GB.

These bits are Intel TXT lockable.

2.7.18 GBSM— Graphics Base of Pre-allocated Memory Register

This register contains the base address of DRAM memory pre-allocated for graphics

data. BIOS determines the base of memory pre-allocated for graphics by subtracting

the graphics data pre-allocated memory size (PCI Device 0, offset 52h, bits 7:4) from

TOLUD (PCI Device 0, offset B0h, bits 15:4).

This register is locked and becomes read only when CMD.LOCK.MEMCONFIG is received

or when ME_SM_LOCK is set to 1.

B/D/F/Type: 0/0/0/PCI

Address Offset: A2–A3h

Reset Value: 0000h

Access: RW-L

Bit Attr

Reset

Value

Description

15:0 RW-L 0000h

TOUUD (TOUUD)

This register contains bits 35:20 of an address one byte above the maximum

DRAM memory above 4 GB that is usable by the operating system.

Configuration software must set this value to TOM minus all EP pre-allocated

memory if reclaim is disabled. If reclaim is enabled, this value must be set to

reclaim limit 64 MB aligned since reclaim limit + 1byte is 64 MB aligned.

Address bits 19:0 are assumed to be 000_0000h for the purposes of address

comparison. The Host interface positively decodes an address towards DRAM

if the incoming address is less than the value programmed in this register

and greater than 4 GB.

All the bits in this register are locked in Intel TXT mode.

B/D/F/Type: 0/0/0/PCI

Address Offset: A4–A7h

Reset Value: 0000_0000h

Access: RW-L, RO

Bit Attr

Reset

Value

Description

31:20 RW-L 000h

Graphics Base of Pre-allocated Memory (GBSM)

This register contains bits 31:20 of the base address of DRAM memory pre-

allocated for graphics. BIOS determines the base of memory pre-allocated

for graphics by subtracting the pre-allocated memory size (PCI Device 0,

offset 52h, bits 6:4) from TOLUD (PCI Device 0, offset B0h, bits 15:4).

This register is locked and becomes Read Only when CMD.LOCK.MEMCONFIG

is received or when ME_SM_LOCK is set to 1.

19:0 RO 00000h Reserved

1 2 ... 53 54 55 56 57 58 59 60 61 62 63 ... 359 360

Comments to this Manuals

No comments

Intel B940 Datasheet Page 58

Comments to this Manuals

Related products and manuals for Processors Intel B940