Intel B940 Datasheet download pdf (Page 66)

Processor Configuration Registers

66 Datasheet, Volume 2

2.8 MCHBAR Registers

Table 2-5. MCHBAR Register Address Map (Sheet 1 of 2)

Address

Offset

Reset

Value

Access

111h CHDECMISC Channel Decode Misc 00h RW-L, RO

200–201h C0DRB0 Channel 0 DRAM Rank Boundary Address 0 0000h RW-L, RO

202–203h C0DRB1 Channel 0 DRAM Rank Boundary Address 1 0000h RW-L, RO

204–205h C0DRB2 Channel 0 DRAM Rank Boundary Address 2 0000h RO, RW-L

206–207h C0DRB3 Channel 0 DRAM Rank Boundary Address 3 0000h RO, RW-L

208–209h C0DRA01 Channel 0 DRAM Rank 0,1 Attribute 0000h RW-L

20A–20Bh C0DRA23 Channel 0 DRAM Rank 2,3 Attribute 0000h RW-L

24D–24Fh C0WRDATACTRL Channel 0 Write Data Control 004111h RW

250–251h C0CYCTRKPCHG Channel 0 CYCTRK PCHG 0000h RO, RW

252–255h C0CYCTRKACT Channel 0 CYCTRK ACT 0000_0000h RW, RO

256–257h C0CYCTRKWR Channel 0 CYCTRK WR 0000h RW

258–25Ah C0CYCTRKRD Channel 0 CYCTRK READ 000000h RO, RW

25B–25Ch C0CYCTRKREFR Channel 0 CYCTRK REFR 0000h RO, RW

265–266h C0PWLRCTRL Channel 0 PWLRCTL 0000h RO, RW

269–26Eh C0REFRCTRL

Channel 0 DRAM Refresh Control 241830000C

30h

RW, RO

271h C0JEDEC Channel 0 JEDEC CTRL 00h RW, RO

298–29Bh C0ODT Channel 0 ODT Matrix 0000_0000h RW, RO

29C–29Fh C0ODTCTRL Channel 0 ODT Control 0000_0000h RW, RO

2B4–2B7h C0DTC

Channel 0 DRAM Throttling Control

0000_0000h

RO, RW-L-K,

RW-L

600–601h C1DRB0 Channel 1 DRAM Rank Boundary Address 0 0000h RW-L, RO

602–603h C1DRB1 Channel 1 DRAM Rank Boundary Address 1 0000h RO, RW-L

604–605h C1DRB2 Channel 1 DRAM Rank Boundary Address 2 0000h RW-L, RO

606–607h C1DRB3 Channel 1 DRAM Rank Boundary Address 3 0000h RW-L, RO

608–609h C1DRA01 Channel 1 DRAM Rank 0,1 Attributes 0000h RW-L

60A–60Bh C1DRA23 Channel 1 DRAM Rank 2,3 Attributes 0000h RW-L

64D–64Fh C1WRDATACTRL Channel 1 Write Data Control 004111h RW

650–651h C1CYCTRKPCHG Channel 1 CYCTRK PCHG 0000h RW, RO

652–655h C1CYCTRKACT Channel 1 CYCTRK ACT 0000_0000h RW, RO

656–657h C1CYCTRKWR Channel 1 CYCTRK WR 0000h RW

658–65Ah C1CYCTRKRD Channel 1 CYCTRK READ 000000h RW, RO

660–663h C1CKECTRL Channel 1 CKE Control 0000_0800h RW, RW-L, RO

69C–69Fh C1ODTCTRL Channel 1 ODT Control 0000_0000h RO, RW

6A4–6A7h C1GTC

Channel 1 Processor Throttling Control

0000_0000h

RW-L-K, RO,

RW-L

6B4–6B7h C1DTC

Channel 1 DRAM Throttling Control

0000_0000h

RO, RW-L-K,

RW-L

C20–C27h SSKPD

Sticky Scratchpad Data 0000_0000_

0000_0000h

RW/P

1 2 ... 61 62 63 64 65 66 67 68 69 70 71 ... 359 360

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Intel B940 Datasheet Page 66

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