Intel B940 Datasheet download pdf (Page 144)

Processor Configuration Registers

144 Datasheet, Volume 2

2.10.40 CTL—Link Control Register

This register allows control of PCI Express link.

B/D/F/Type: 0/1/0/PCI

Address Offset: B0–B1h

Reset Value: 0000h

Access: RO, RW, RW-SC

Bit Attr

Reset

Value

Description

15:12 RO 0000b Reserved

11 RW 0b

Link Autonomous Bandwidth Interrupt Enable (LABIE)

Link Autonomous Bandwidth Interrupt Enable – When Set, this bit enables

the generation of an interrupt to indicate that the Link Autonomous

Bandwidth Status bit has been Set.

This bit is not applicable and is reserved for Endpoint devices, PCI Express to

PCI/PCI-X bridges, and Upstream Ports of Switches.

Devices that do not implement the Link Bandwidth Notification capability

must hardwire this bit to 0b.

10 RW 0b

Link Bandwidth Management Interrupt Enable (LBMIE)

Link Bandwidth Management Interrupt Enable – When Set, this bit enables

the generation of an interrupt to indicate that the Link Bandwidth

Management Status bit has been Set.

This bit is not applicable and is reserved for Endpoint devices, PCI Express to

PCI/PCI-X bridges, and Upstream Ports of Switches.

9RW 0b

Hardware Autonomous Width Disable (HAWD)

Hardware Autonomous Width Disable - When Set, this bit disables hardware

from changing the Link width for reasons other than attempting to correct

unreliable Link operation by reducing Link width.

Devices that do not implement the ability autonomously to change Link width

are permitted to hardwire this bit to 0b.

8RO 0b

Enable Clock Power Management (ECPM)

Applicable only for form factors that support a "Clock Request" (CLKREQ#)

mechanism, this enable functions as follows:

0 = Clock power management is disabled and device must hold CLKREQ#

signal low

1 = When this bit is set to 1 the device is permitted to use CLKREQ# signal

to power manage link clock according to protocol defined in appropriate

form factor specification.

The Reset Value of this field is 0b. Components that do not support Clock

Power Management (as indicated by a 0b value in the Clock Power

Management bit of the Link Capabilities Register) must hardwire this bit to

0b.

7RW 0b

Extended Synch (ES)

0 = Standard Fast Training Sequence (FTS).

1 = Forces the transmission of additional ordered sets when exiting the L0s

state and when in the Recovery state. This mode provides external

devices (such as, logic analyzers) monitoring the Link time to achieve bit

and symbol lock before the link enters L0 and resumes communication.

This is a test mode only and may cause other undesired side effects

such as buffer overflows or underruns.

6RW 0b

Common Clock Configuration (CCC)

0 = Indicates that this component and the component at the opposite end of

this Link are operating with asynchronous reference clock.

1 = Indicates that this component and the component at the opposite end of

this Link are operating with a distributed common reference clock.

The state of this bit affects the L0s Exit Latency reported in LCAP[14:12] and

the N_FTS value advertised during link training. See PEGL0SLAT at offset

22Ch.

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Intel B940 Datasheet Page 144

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