Intel B940 Datasheet download pdf (Page 34)

Processor Configuration Registers

34 Datasheet, Volume 2

2.2.6 Graphics Memory Address Ranges

The processor can be programmed to direct memory accesses to IGD when addresses

are within any of five ranges specified using registers in the processor Device 2

configuration space.

1. The Graphics Memory Aperture Base Register (GMADR) is used to access graphics

memory allocated using the graphics translation table.

2. The Graphics Translation Table Base Register (GTTADR) is used to access the

translation table and graphics control registers.

3. This is part of GTTMMADR register.

These ranges can reside above the Top-of-Low-DRAM and below High BIOS and APIC

address ranges. They MUST reside above the top of memory (TOLUD) and below 4 GB

so they do not steal any physical DRAM memory space.

Alternatively, these ranges can reside above 4 GB, similar to other BARs which are

larger than 32 bits in size.

GMADR is a Prefetchable range in order to apply USWC attribute (from the processor

point of view) to that range. The USWC attribute is used by the processor for write

combining.

2.2.6.1 IOBAR Mapped Access to Device 2 MMIO Space

Device 2, integrated graphics device, contains an IOBAR register. If Device 2 is

enabled, then IGD registers or the GTT table can be accessed using this IOBAR. The

IOBAR is composed of an index register and a data register.

MMIO_Index — MMIO_INDEX is a 32 bit register. An IO write to this port loads the

offset of the MMIO register or offset into the GTT that needs to be accessed. An IO

Read returns the current value of this register. See IOBAR rules for detailed

information.

MMIO_Data — MMIO_DATA is a 32 bit register. An IO write to this port is re-directed

to the MMIO register pointed to by the MMIO-index register. An IO read to this port is

re-directed to the MMIO register pointed to by the MMIO-index register. See IOBAR

rules for detailed information.

The result of accesses through IOBAR can be:

• Accesses directed to the GTT table. (that is, route to DRAM)

• Accesses to internal graphics registers with the processor (that is, route to internal

configuration bus)

• Accesses to internal graphics display registers now located within the PCH. (that is,

route to DMI).

Note: GTT table space writes (GTTADR) are supported through this mapping mechanism.

This mechanism to access internal graphics MMIO registers must not be used to access

VGA IO registers which are mapped through the MMIO space. VGA registers must be

accessed directly through the dedicated VGA I/O ports.

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Intel B940 Datasheet Page 34