Intel B940 Datasheet download pdf (Page 3)

Datasheet, Volume 2 3

Contents

1Introduction............................................................................................................13

2 Processor Configuration Registers...........................................................................15

2.1 Register Terminology.........................................................................................15

2.2 System Address Map .........................................................................................17

2.2.1 Legacy Address Range.........................................................................19

2.2.1.1 DOS Range (0000_0000h – 0009_FFFFh).....................................19

2.2.1.2 Legacy Video Area (000A_0000h – 000B_FFFFh)........................... 19

2.2.1.3 PAM (000C_0000h-000F_FFFFh) .................................................20

2.2.2 Main Memory Address Range (1MB – TOLUD)..........................................21

2.2.2.1 ISA Hole (15 MB – 16 MB) .........................................................21

2.2.2.2 TSEG ......................................................................................22

2.2.2.3 Protected Memory Range (PMR) – (programmable) .......................22

2.2.2.4 DRAM Protected Range (DPR).....................................................23

2.2.2.5 Pre-allocated Memory ...............................................................23

2.2.2.6 Graphics Stolen Spaces .............................................................23

2.2.2.7 Intel

Management Engine (Intel

ME) UMA ...............................24

2.2.2.8 PCI Memory Address Range (TOLUD – 4 GB)................................24

2.2.2.9 APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ...................26

2.2.2.10 High BIOS Area ........................................................................26

2.2.3 Main Memory Address Space (4 GB to TOUUD)........................................27

2.2.3.1 Programming Model ..................................................................28

2.2.4 PCI Express* Configuration Address Space .............................................33

2.2.5 PCI Express* Graphics Attach (PEG) ......................................................33

2.2.6 Graphics Memory Address Ranges .........................................................34

2.2.6.1 IOBAR Mapped Access to Device 2 MMIO Space ............................34

2.2.7 System Management Mode (SMM).........................................................35

2.2.8 SMM and VGA Access through GTT TLB .................................................35

2.2.9 I/O Address Space ..............................................................................35

2.2.9.1 PCI Express* I/O Address Mapping..............................................36

2.3 Configuration Process and Registers.....................................................................37

2.3.1 Platform Configuration Structure ...........................................................37

2.4 Configuration Mechanisms..................................................................................38

2.4.1 Standard PCI Configuration Mechanism..................................................38

2.4.2 PCI Express* Enhanced Configuration Mechanism....................................39

2.4.3 Routing Configuration Accesses.............................................................40

2.4.4 Internal Device Configuration Accesses ..................................................41

2.4.5 Bridge Related Configuration Accesses ...................................................42

2.4.5.1 PCI Express* Configuration Accesses...........................................42

2.4.5.2 DMI Configuration Accesses .......................................................43

2.5 Processor Register Introduction...........................................................................43

2.6 I/O Mapped Registers ........................................................................................44

2.7 PCI Express* Device 0 Registers..........................................................................45

2.7.1 VID—Vendor Identification Register .......................................................46

2.7.2 DID—Device Identification Register........................................................46

2.7.3 PCICMD—PCI Command Register ..........................................................47

2.7.4 PCISTS—PCI Status Register ................................................................48

2.7.5 RID—Revision Identification..................................................................49

2.7.6 CC—Class Code Register ......................................................................49

2.7.7 MLT—Master Latency Timer Register......................................................49

2.7.8 HDR—Header Type Register..................................................................50

2.7.9 SVID—Subsystem Vendor Identification Register.....................................50

2.7.10 SID—Subsystem Identification Register..................................................51

2.7.11 PXPEPBAR—PCI Express Egress Port Base Address Register ......................51

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Intel B940 Datasheet Page 3

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