Intel B940 Datasheet Page 169
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Datasheet, Volume 2 169
Processor Configuration Registers
2.12.12 DMIVCPRSTS—DMI VCp Resource Status Register
This register reports the Virtual Channel specific status.
2.12.13 DMIESD—DMI Element Self Description Register
This register provides information about the root complex element containing this Link
Declaration Capability.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 32–33h
Reset Value: 0002h
Access: RO
Bit Attr
Reset
Value
Description
15:2 RO 0000h
Reserved: Reserved and Zero for future R/WC/S implementations. Software
must use 0 for writes to these bits.
1RO 1b
Virtual Channel private Negotiation Pending (VCPNP)
0 = The VC negotiation is complete.
1 = The VC resource is still in the process of negotiation (initialization or
disabling).
Software may use this bit when enabling or disabling the VC. This bit
indicates the status of the process of Flow Control initialization. It is set by
default on Reset, as well as whenever the corresponding Virtual Channel is
Disabled or the Link is in the DL_Down state. It is cleared when the link
successfully exits the FC_INIT2 state.
Before using a Virtual Channel, software must check whether the VC
Negotiation Pending fields for that Virtual Channel are cleared in both
Components on a Link.
0RO 0bReserved
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 44–47h
Reset Value: 01000202h
Access: RO, RWO
Bit Attr
Reset
Value
Description
31:24 RO 01h
Port Number (PORTNUM)
This field specifies the port number associated with this element with respect
to the component that contains this element. This port number value is
utilized by the egress port of the component to provide arbitration to this
Root Complex Element.
23:16 RW-O 00h
Component ID (CID)
This field identifies the physical component that contains this Root Complex
Element.
BIOS Requirement: Must be initialized according to guidelines in the PCI
Express* Isochronous/Virtual Channel Support Hardware Programming
Specification (HPS).
15:8 RO 02h
Number of Link Entries (NLE)
This field indicates the number of link entries following the Element Self
Description. This field reports 2 (one for the processor egress port to main
memory and one to egress port belonging to PCH on other side of internal
link).
7:4 RO 0h Reserved
3:0 RO 2h
Element Type (ETYP)
This field indicates the type of the Root Complex Element.
Value of 2h represents an Internal Root Complex Link (DMI).
- Datasheet – Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
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- Datasheet, Volume 2 5 5
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- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Datasheet, Volume 2 11 11
- Revision History 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.2.1 Legacy Address Range 19
- Datasheet, Volume 2 21 21
- 2.2.2.2 TSEG 22
- 2.2.2.5 Pre-allocated Memory 23
- 2.2.2.7 Intel 24
- Management Engine (Intel 24
- ME) UMA 24
- Datasheet, Volume 2 25 25
- 2.2.2.10 High BIOS Area 26
- Datasheet, Volume 2 27 27
- 2.2.3.1 Programming Model 28
- HOST/SYSTEM VIEW 29
- PHYSICAL MEMORY 29
- (DRAM CONTROLLER VIEW) 29
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.2.9 I/O Address Space 35
- 36 Datasheet, Volume 2 36
- Datasheet, Volume 2 37 37
- 2.4 Configuration Mechanisms 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.6 I/O Mapped Registers 44
- 2.7.6 CC—Class Code Register 49
- TXT Lockable 54
- 1:0 to 11b 56
- 4) from 58
- B0h, bits 15:4) 58
- 2.8 MCHBAR Registers 66
- 00h RW 67
- Register Symbol Register Name 67
- 208–209h 73
- 20A–20Bh 74
- 24D–24Fh 74
- 250-251h 75
- 252–255h 76
- 256–257h 77
- 258–25Ah 77
- 269–26Eh 79
- 298–29Bh 82
- 29C–29Fh 84
- 2B4–2B7h 84
- 600–601h 86
- 602–603h 86
- 604–605h 86
- 64D–64Fh 88
- 650–651h 88
- 652–655h 89
- 656–657h 90
- 658–65Ah 90
- 660–663h 91
- 6B4–6B7h 93
- C20–C27h 94
- 1001–1002h 94
- 1004–1005h 95
- 101E–101Fh 100
- Register 107
- 10EC–10EDh 108
- 2C20–2C22h 109
- 2.9 EPBAR Registers 110
- 2.10 PCI Device 1 Registers 115
- PCI device 117
- Port Command Register 140
- 11:10 RW-O 11b 143
- OS's during run time 155
- 104–107h 156
- 108–10Bh 157
- 10C–10Dh 157
- 110–113h 158
- 23 RO 0b Reserved 158
- 114–117h 158
- 11A–11Bh 159
- 2.12 DMIBAR Registers 161
- Declaration Capability 169
- 2.13.6 CC—Class Code Register 177
- Range Address Register 179
- GMADR register 180
- 2.14 Device 2 I/O Registers 183
- 100–107h 211
- 108–10Fh 212
- 200–20Fh 214
- F00–F03h 215
- F04–F07h 216
- Dedication 217
- F08–F0Bh 218
- FFC–FFFh 219
- 2.16 DMI VC1 REMAP Registers 221
- 2.17.2 GFXPLL1—GFX PLL BIOS 254
- 2.18 GFXVTBAR Registers 255
- Address Register 281
- 2.19 PCI Device 6 Registers 288
- 2.19.45 RSTS—Root Status 327
- 2.21 Intel 332
- Specific Registers 332
- 110–117h 333
- 330–337h 333
- Lower Half Register 334
- Upper Half Register 334
- QuickPath Architecture 335
- System Address Decode 335
- Register Description 335
- QPI Link 0 Registers 340
- QPI Physical 0 Registers 341
- 3.4 PCI Standard Registers 342
- 3.4.4 CCR—Class Code Register 344
- Identification Register 345
- 3.4.7 PCICMD—Command Register 346
- 3.5.1 MAX_RTIDS 349
- 3.6.1 SAD_PAM0123 349
- 3.6.2 SAD_PAM456 351
- 3.6.3 SAD_HEN 352
- 3.6.4 SAD_SMRAM 353
- 3.6.5 SAD_PCIEXBAR 354
- 3.7 Intel 356
- QPI Link Registers 356
- 3.8 Intel 357
- QPI Physical Layer Registers 357
- 360 Datasheet, Volume 2 360
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