Intel B940 Datasheet download pdf (Page 24)

Processor Configuration Registers

24 Datasheet, Volume 2

2.2.2.6.3 Shadow GTT Stolen Space (SGSM)

Shadow GSM will be only used once internal GFX and VT-d translations are enabled.

The purpose of shadow GSM is to provide a physical space to hardware, where VT-d

translation for PTE updates can be made on the fly and re-written back into physical

memory.

2.2.2.7 Intel

Management Engine (Intel

ME) UMA

ME (the iAMT Manageability Engine) can be allocated UMA memory. ME memory is

“stolen” from the top of the host address map. The ME stolen memory base is

calculated by subtracting the amount of memory stolen by the Manageability Engine

from TOM.

Only ME can access this space; it is not accessible by or coherent with any processor

side accesses.

2.2.2.8 PCI Memory Address Range (TOLUD – 4 GB)

This address range, from the top of low usable DRAM (TOLUD) to 4 GB is normally

mapped to the DMI Interface.

Device 0 exceptions are:

1. Addresses decoded to the egress port registers (PXPEPBAR)

2. Addresses decoded to the memory mapped range for internal processor registers

(GMCHBAR)

3. Addresses decoded to the registers associated with the processor/PCH Serial

Interconnect (DMI) register memory range. (DMIBAR)

For each PCI Express port, there are two exceptions to this rule:

1. Addresses decoded to the PCI Express Memory Window defined by the MBASE1,

MLIMIT1, registers are mapped to PCI Express.

2. Addresses decoded to the PCI Express prefetchable Memory Window defined by the

PMBASE1, PMLIMIT1, registers are mapped to PCI Express.

In integrated graphics configurations, there are exceptions to this rule:

1. Addresses decode to the internal graphics translation window (GMADR)

2. Addresses decode to the Internal graphics translation table or IGD registers.

(GTTMMADR)

In a VT enable configuration, there are exceptions to this rule:

1. Addresses decoded to the memory mapped window to DMI VC1 VT remap engine

registers (DMIVC1BAR)

2. Addresses decoded to the memory mapped window to Graphics VT remap engine

registers (GFXVTBAR)

3. Addresses decoded to the memory mapped window to PEG/DMI/ME VC0 VT remap

engine registers (VTDPVC0BAR)

4. TCm accesses (to ME stolen memory) from PCH do not go through VT remap

engines.

Some of the MMIO Bars may be mapped to this range or to the range above TOUUD.

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Intel B940 Datasheet Page 24

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