Intel B940 Datasheet download pdf (Page 263)

Datasheet, Volume 2 263

Processor Configuration Registers

26 RO 0b

Queued Invalidation Enable (QIE)

This field is valid only for implementations supporting queued invalidations.

Software writes to this field to enable or disable queued invalidations.

0 = Disable queued invalidations.

1 = Enable use of queued invalidations.

Hardware reports the status of queued invalidation enable operation through

QIES field in the Global Status register.

Refer to the VTd specification for software requirements for

enabling/disabling queued invalidations.

The value returned on a read of this field is undefined.

25 RO 0b

Interrupt Remapping Enable (IRE)

This field is valid only for implementations supporting interrupt remapping.

0 = Disable interrupt-remapping hardware

1 = Enable interrupt-remapping hardware

Hardware reports the status of the interrupt remapping enable operation

through the IRES field in the Global Status register.

There may be active interrupt requests in the platform when software

updates this field. Hardware must enable or disable interrupt-remapping logic

only at deterministic transaction boundaries, so that any in-flight interrupts

are either subject to remapping or not at all.

Hardware implementations must drain any in-flight interrupts requests

queued in the Root-Complex before completing the interrupt-remapping

enable command and reflecting the status of the command through the IRES

field in the Global Status register.

The value returned on a read of this field is undefined.

24 RO 0b

Set Interrupt Remap Table Pointer (SIRTP)

This field is valid only for implementations supporting interrupt-remapping.

Software sets this field to set/update the interrupt remapping table pointer

used by hardware. The interrupt remapping table pointer is specified through

the Interrupt Remapping Table Address register.

Hardware reports the status of the interrupt remapping table pointer set

operation through the IRTPS field in the Global Status register.

The interrupt remap table pointer set operation must be performed before

enabling or re-enabling (after disabling) interrupt-remapping hardware

through the IRE field.

After an interrupt remap table pointer set operation, software must globally

invalidate the interrupt entry cache. This is required to ensure hardware uses

only the interrupt-remapping entries referenced by the new interrupt remap

table pointer, and not any stale cached entries.

While interrupt remapping is active, software may update the interrupt

remapping table pointer through this field. However, to ensure valid in-flight

interrupt requests are deterministically remapped, software must ensure that

the structures referenced by the new interrupt remap table pointer are

programmed to provide the same remapping results as the structures

referenced by the previous interrupt remap table pointer.

Clearing this bit has no effect. The value returned on a read of this field is

undefined.

B/D/F/Type: 0/2/0/GFXVTBAR

Address Offset: 18–1Bh

Reset Value: 00000000h

Access: W, RO, RW

Bit Attr

Reset

Value

Description

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Intel B940 Datasheet Page 263

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