Intel B940 Datasheet download pdf (Page 52)

Processor Configuration Registers

52 Datasheet, Volume 2

2.7.12 MCHBAR—MCH Memory Mapped Register Range Base

This is the base address for the processor memory mapped configuration space. There

is no physical memory within this 16 KB window that can be addressed. The 16 KB

reserved by this register does not alias to any PCI 2.3 compliant memory mapped

space. On reset, the processor MMIO memory mapped configuation space is disabled

and must be enabled by writing a 1 to MCHBAREN [Device 0, offset48h, bit 0].

All the bits in this register are locked in Intel TXT mode.

The register space contains memory control, initialization, timing, and buffer strength

registers — clocking registers and power and thermal management registers. The

16 KB space reserved by the MCHBAR register is not accessible during Intel TXT mode

of operation or if the ME security lock is asserted (MESMLCK.ME_SM_lock at PCI device

0, function 0, offset F4h) except for the following offset ranges.

02B8h to 02BFh: Channel 0 Throttle Counter Status Registers

06B8h to 06BFh: Channel 1 Throttle Counter Status Registers

0CD0h to 0CFFh: Thermal Sensor Control Registers

3000h to 3FFFh: Unlocked registers for future expansion

B/D/F/Type: 0/0/0/PCI

Address Offset: 48–4Fh

Reset Value: 0000_0000_0000_0000h

Access: RW-L, RO

Bit Attr

Reset

Value

Description

63:36 RO 0000000h Reserved

35:14 RW-L 000000h

MCH Memory Mapped Base Address (MCHBAR)

This field corresponds to bits 35:4 of the base address processor memory

mapped configuration space. BIOS will program this register resulting in a

base address for a 16 KB block of contiguous memory address space. This

first 64 GB of addressable memory space. System Software uses this base

address to program the processor memory mapped register set. All the bits

in this register are locked in Intel TXT mode.

13:1 RO 0000h Reserved

0RW-L 0b

MCHBAR Enable (MCHBAREN)

0 = Disable. MCHBAR is disabled and does not claim any memory

1 = Enable. MCHBAR memory mapped accesses are claimed and decoded

appropriately

This register is locked by Intel TXT.

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 359 360

No comments

Intel B940 Datasheet Page 52