Intel B940 Datasheet Page 168
- Page / 360
- Table of contents
- BOOKMARKS
Rated. / 5. Based on customer reviews
Processor Configuration Registers
168 Datasheet, Volume 2
2.12.11 DMIVCPRCTL—DMI VCp Resource Control Register
This register controls the resources associated with the DMI Private Channel.
B/D/F/Type: 0/0/0/DMIBAR
Address Offset: 2C–2Fh
Reset Value: 0000_0000h
Access: RW, RO
Bit Attr
Reset
Value
Description
31 RW 0b
Virtual Channel Enable (VCE)
0 = Virtual Channel is disabled.
1 = Virtual Channel is enabled. See exceptions below.
Software must use the VC Negotiation Pending bit to check whether the VC
negotiation is complete. When VC Negotiation Pending bit is cleared, a 1 read
from this VC Enable bit indicates that the VC is enabled (Flow Control
Initialization is completed for the PCI Express port). A 0 read from this bit
indicates that the Virtual Channel is currently disabled.
BIOS Requirement:
1. To enable a Virtual Channel, the VC Enable bits for that Virtual Channel
must be set in both Components on a Link.
2. To disable a Virtual Channel, the VC Enable bits for that Virtual Channel
must be cleared in both Components on a Link.
3. Software must ensure that no traffic is using a Virtual Channel at the
time it is disabled.
4. Software must fully disable a Virtual Channel in both Components on a
Link before re-enabling the Virtual Channel.
30:27 RO 0h Reserved
26:24 RW 010b
Virtual Channel ID (VCID)
Assigns a VC ID to the VC resource. This field can not be modified when the
VC is already enabled.
23:8 RO 0000h Reserved
7:1 RW 00h
Traffic Class / Virtual Channel Map (TCVCM)
This field indicates the TCs that are mapped to the VC resource. This field is
valid for all Functions.
Bit locations within this field correspond to TC values. For example, when bit
7 is Set in this field, TC7 is mapped to this VC resource. When more than 1
bit in this field is set, it indicates that multiple TCs are mapped to the VC
resource.
To remove one or more TCs from the TC/VC Map of an enabled VC, software
must ensure that no new or outstanding transactions with the TC labels are
targeted at the given Link.
BIOS Requirement: Program this field, including bit 0, with the value
01000100b, which maps TC2 and TC6 to VCp.
0RO 0b
Traffic Class 0 / Virtual Channel Map (TC0VCM)
Traffic Class 0 is always routed to VC0.
- Datasheet – Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Datasheet, Volume 2 11 11
- Revision History 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.2.1 Legacy Address Range 19
- Datasheet, Volume 2 21 21
- 2.2.2.2 TSEG 22
- 2.2.2.5 Pre-allocated Memory 23
- 2.2.2.7 Intel 24
- Management Engine (Intel 24
- ME) UMA 24
- Datasheet, Volume 2 25 25
- 2.2.2.10 High BIOS Area 26
- Datasheet, Volume 2 27 27
- 2.2.3.1 Programming Model 28
- HOST/SYSTEM VIEW 29
- PHYSICAL MEMORY 29
- (DRAM CONTROLLER VIEW) 29
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.2.9 I/O Address Space 35
- 36 Datasheet, Volume 2 36
- Datasheet, Volume 2 37 37
- 2.4 Configuration Mechanisms 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.6 I/O Mapped Registers 44
- 2.7.6 CC—Class Code Register 49
- TXT Lockable 54
- 1:0 to 11b 56
- 4) from 58
- B0h, bits 15:4) 58
- 2.8 MCHBAR Registers 66
- 00h RW 67
- Register Symbol Register Name 67
- 208–209h 73
- 20A–20Bh 74
- 24D–24Fh 74
- 250-251h 75
- 252–255h 76
- 256–257h 77
- 258–25Ah 77
- 269–26Eh 79
- 298–29Bh 82
- 29C–29Fh 84
- 2B4–2B7h 84
- 600–601h 86
- 602–603h 86
- 604–605h 86
- 64D–64Fh 88
- 650–651h 88
- 652–655h 89
- 656–657h 90
- 658–65Ah 90
- 660–663h 91
- 6B4–6B7h 93
- C20–C27h 94
- 1001–1002h 94
- 1004–1005h 95
- 101E–101Fh 100
- Register 107
- 10EC–10EDh 108
- 2C20–2C22h 109
- 2.9 EPBAR Registers 110
- 2.10 PCI Device 1 Registers 115
- PCI device 117
- Port Command Register 140
- 11:10 RW-O 11b 143
- OS's during run time 155
- 104–107h 156
- 108–10Bh 157
- 10C–10Dh 157
- 110–113h 158
- 23 RO 0b Reserved 158
- 114–117h 158
- 11A–11Bh 159
- 2.12 DMIBAR Registers 161
- Declaration Capability 169
- 2.13.6 CC—Class Code Register 177
- Range Address Register 179
- GMADR register 180
- 2.14 Device 2 I/O Registers 183
- 100–107h 211
- 108–10Fh 212
- 200–20Fh 214
- F00–F03h 215
- F04–F07h 216
- Dedication 217
- F08–F0Bh 218
- FFC–FFFh 219
- 2.16 DMI VC1 REMAP Registers 221
- 2.17.2 GFXPLL1—GFX PLL BIOS 254
- 2.18 GFXVTBAR Registers 255
- Address Register 281
- 2.19 PCI Device 6 Registers 288
- 2.19.45 RSTS—Root Status 327
- 2.21 Intel 332
- Specific Registers 332
- 110–117h 333
- 330–337h 333
- Lower Half Register 334
- Upper Half Register 334
- QuickPath Architecture 335
- System Address Decode 335
- Register Description 335
- QPI Link 0 Registers 340
- QPI Physical 0 Registers 341
- 3.4 PCI Standard Registers 342
- 3.4.4 CCR—Class Code Register 344
- Identification Register 345
- 3.4.7 PCICMD—Command Register 346
- 3.5.1 MAX_RTIDS 349
- 3.6.1 SAD_PAM0123 349
- 3.6.2 SAD_PAM456 351
- 3.6.3 SAD_HEN 352
- 3.6.4 SAD_SMRAM 353
- 3.6.5 SAD_PCIEXBAR 354
- 3.7 Intel 356
- QPI Link Registers 356
- 3.8 Intel 357
- QPI Physical Layer Registers 357
- 360 Datasheet, Volume 2 360
Related products and manuals for Processors Intel B940
Processors Intel core 2 Duo T5850 Specifications
(292 pages)
(292 pages)
Processors Intel AT80569KJ073N Datasheet
(102 pages)
(102 pages)
© 2020, manymanuals.com. All rights reserved. | 0.523 s |
Manymanuals.com
Manymanuals.de
Manymanuals.fr
Manymanuals.it
Manymanuals.pl
Manymanuals.cz
Manymanuals.es
Manymanuals-pt.com
Comments to this Manuals