Intel B940 Datasheet download pdf (Page 38)

Processor Configuration Registers

38 Datasheet, Volume 2

2.4 Configuration Mechanisms

The GMCH is the originator of configuration cycles. Internal to the GMCH transactions

received through both configuration mechanisms are translated to the same format.

2.4.1 Standard PCI Configuration Mechanism

The following is the mechanism for translating GMCH I/O bus cycles to configuration

cycles.

The PCI specification defines a slot based "configuration space" that allows each device

to contain up to eight functions with each function containing up to 256, 8-bit

configuration registers. The PCI specification defines two bus cycles to access the PCI

configuration space: Configuration Read and Configuration Write. Memory and I/O

spaces are supported directly by the GMCH. Configuration space is supported by a

mapping mechanism implemented within the GMCH.

The configuration access mechanism makes use of the CONFIG_ADDRESS Register (at

I/O address 0CF8h though 0CFBh) and CONFIG_DATA Register (at I/O address 0CFCh

though 0CFFh). To reference a configuration register, a DW I/O write cycle is used to

place a value into CONFIG_ADDRESS that specifies the PCI bus, the device on that bus,

the function within the device and a specific configuration register of the device

function being accessed. CONFIG_ADDRESS[31] must be 1 to enable a configuration

cycle. CONFIG_DATA then becomes a window into the four bytes of configuration space

specified by the contents of CONFIG_ADDRESS. Any read or write to CONFIG_DATA will

result in the GMCH translating the CONFIG_ADDRESS into the appropriate

configuration cycle.

The GMCH is responsible for translating and routing the GMCH’s I/O accesses to the

CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH configuration

registers, DMI or PCI Express.

Table 2-3. Device Number Assignment for Internal Processor Devices

Processor Function Device Number

Host Bridge/DRAM Controller Device 0

Host-to-PCI Express* Bridge (virtual P2P) Device 1

Internal Graphics Device Device 2

Secondary Host-to-PCI Express Bridge

(Device 6 is not supported on all SKUs.)

Device 6

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 359 360

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Intel B940 Datasheet Page 38