Intel B940 Datasheet download pdf (Page 20)

Processor Configuration Registers

20 Datasheet, Volume 2

Non-SMM-mode processor accesses to this range are considered to be to the Video

Buffer Area as described above. The processor will route these accesses on the non-

coherent (NCS or NCB) channels.

The processor always positively decodes internally mapped devices, namely the IGD

and PCI-Express. Subsequent decoding of regions mapped to PCI Express or the DMI

Interface depends on the Legacy VGA configuration bits (VGA Enable and MDAP). This

region is also the default for SMM space.

Compatible SMRAM Address Range (000A_0000h – 000B_FFFFh)

Unlike FSB platforms, the Intel

Core™ i5-600, i3-500 Desktop processor series and

Intel

Pentium

desktop processor 6000 series see no SMM indication with processor

accesses. When compatible SMM space is enabled, SMM-mode processor accesses to

this range route to physical system DRAM at 000A_0000h – 000B_FFFFh. The

processor performs the decode and routes the access to physical system DRAM. In

other words, an SMM-mode processor access to this range will be sent on the HOM QPI

channel.

PCI Express and DMI originated cycles to enabled SMM space are not allowed and are

considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI

initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port.

Monochrome Adapter (MDA) Range (000B_0000h – 000B_7FFFh)

Legacy support requires the ability to have a second graphics controller (monochrome)

in the system. Accesses in the standard VGA range are forwarded to IGD, PCI-Express,

or the DMI Interface (depending on configuration bits). Since the monochrome adapter

may be mapped to any of these devices, the processor must decode cycles in the MDA

range (000B_0000h – 000B_7FFFh) and forward either to IGD, PCI-Express, or the DMI

Interface. This capability is controlled by a VGA steering bits and the legacy

configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the

processor decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards

them to the either IGD, PCI-Express, and/or the DMI Interface.

2.2.1.3 PAM (000C_0000h-000F_FFFFh)

The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory

Area. Each section has Read enable and Write enable attributes. The processor

documentation will now contain the registers and decode rules/restrictions.

The PAM registers have moved to the processor. For the PAM register details, refer to

processor documentation.

• ISA Expansion Area (000C_0000h – 000D_FFFFh)

• Extended System BIOS Area (000E_0000h – 000E_FFFFh)

• System BIOS Area (000F_0000h – 000F_FFFFh)

The processor contains the PAM registers and the GMCH has no knowledge of the

appropriate destination (DRAM or DMI) by sending the request on HOM or NCS/NCB.

Snooped accesses from PCI Express or DMI to this region are snooped on QPI.

Non-snooped accesses from PCI Express or DMI to this region are always sent to

DRAM. Graphics translated requests to this region are not allowed. If such a mapping

error occurs, the request will be routed to 000C_0000h. Writes will have the byte

enables de-asserted.

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Intel B940 Datasheet Page 20

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