Intel B940 Datasheet Page 7
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Datasheet, Volume 2 7
2.13.8 MLT2—Master Latency Timer Register.................................................. 178
2.13.9 HDR2—Header Type Register.............................................................. 178
2.13.10 GTTMMADR—Graphics Translation Table, Memory Mapped Range Address
Register........................................................................................... 179
2.13.11 GMADR—Graphics Memory Range Address Register ............................... 180
2.13.12 IOBAR—I/O Base Address Register ...................................................... 181
2.13.13 SVID2—Subsystem Vendor Identification Register ................................. 181
2.13.14 SID2—Subsystem Identification Register.............................................. 182
2.13.15 ROMADR—Video BIOS ROM Base Address Register ................................ 182
2.13.16 INTRPIN—Interrupt Pin Register.......................................................... 182
2.13.17 MINGNT—Minimum Grant Register ...................................................... 183
2.13.18 MAXLAT—Maximum Latency Register................................................... 183
2.14 Device 2 I/O Registers..................................................................................... 183
2.14.1 Index—MMIO Address Register ........................................................... 184
2.14.2 Data—MMIO Data Register ................................................................. 184
2.15 DMI and PEG VC0/VCp Remap Registers............................................................. 185
2.15.1 VER_REG—Version Register................................................................ 186
2.15.2 CAP_REG—Capability Register............................................................. 187
2.15.3 ECAP_REG—Extended Capability Register............................................. 190
2.15.4 GCMD_REG—Global Command Register................................................ 191
2.15.5 GSTS_REG—Global Status Register...................................................... 194
2.15.6 RTADDR_REG—Root-Entry Table Address Register................................. 195
2.15.7 CCMD_REG—Context Command Register.............................................. 196
2.15.8 FSTS_REG—Fault Status Register........................................................ 198
2.15.9 FECTL_REG—Fault Event Control Register............................................. 199
2.15.10 FEDATA_REG—Fault Event Data Register.............................................. 200
2.15.11 FEADDR_REG—Fault Event Address Register......................................... 200
2.15.12 FEUADDR_REG—Fault Event Upper Address Register.............................. 200
2.15.13 AFLOG_REG—Advanced Fault Log Register ........................................... 201
2.15.14 PMEM_REG—Protected Memory Enable Register .................................... 202
2.15.15 PLMBASE_REG—Protected Low-Memory Base Register ........................... 203
2.15.16 PLMLIMIT_REG—Protected Low-Memory Limit Register........................... 204
2.15.17 PHMBASE_REG—Protected High-Memory Base Register.......................... 205
2.15.18 PHMLIMIT_REG—Protected High-Memory Limit Register ......................... 206
2.15.19 IQH_REG—Invalidation Queue Head Register ........................................ 206
2.15.20 IQT_REG—Invalidation Queue Tail Register........................................... 207
2.15.21 IQA_REG—Invalidation Queue Address Register .................................... 207
2.15.22 ICS_REG—Invalidation Completion Status Register................................ 208
2.15.23 IECTL_REG—Invalidation Event Control Register.................................... 208
2.15.24 IEDATA_REG—Invalidation Event Data Register..................................... 209
2.15.25 IEADDR_REG—Invalidation Event Address Register................................ 209
2.15.26 IEUADDR_REG—Invalidation Event Upper Address Register..................... 210
2.15.27 IRTA_REG—Interrupt Remapping Table Address Register........................ 210
2.15.28 IVA_REG—Invalidate Address Register................................................. 211
2.15.29 IOTLB_REG—IOTLB Invalidate Register................................................ 212
2.15.30 FRCD_REG—Fault Recording Registers ................................................. 214
2.15.31 VTCMPLRESR—VT Completion Resource Dedication................................ 215
2.15.32 VTFTCHARBCTL—VC0/VCp VTd Fetch Arbiter Control.............................. 216
2.15.33 PEGVTCMPLRESR—PEG VT Completion Resource Dedication.................... 217
2.15.34 VTPOLICY—DMA Remap Engine Policy Control....................................... 219
2.16 DMI VC1 REMAP Registers................................................................................ 221
2.16.1 VER_REG—Version Register................................................................ 222
2.16.2 CAP_REG—Capability Register............................................................. 223
2.16.3 ECAP_REG—Extended Capability Register............................................. 225
2.16.4 GCMD_REG—Global Command Register................................................ 227
2.16.5 GSTS_REG—Global Status Register...................................................... 230
- Datasheet – Volume 2 1
- Legal Lines and Disclaimers 2
- Contents 3
- 4 Datasheet, Volume 2 4
- Datasheet, Volume 2 5 5
- 6 Datasheet, Volume 2 6
- Datasheet, Volume 2 7 7
- 8 Datasheet, Volume 2 8
- Datasheet, Volume 2 9 9
- 10 Datasheet, Volume 2 10
- Datasheet, Volume 2 11 11
- Revision History 12
- 1 Introduction 13
- Introduction 14
- 2 Processor Configuration 15
- 2.2 System Address Map 17
- 18 Datasheet, Volume 2 18
- 2.2.1 Legacy Address Range 19
- Datasheet, Volume 2 21 21
- 2.2.2.2 TSEG 22
- 2.2.2.5 Pre-allocated Memory 23
- 2.2.2.7 Intel 24
- Management Engine (Intel 24
- ME) UMA 24
- Datasheet, Volume 2 25 25
- 2.2.2.10 High BIOS Area 26
- Datasheet, Volume 2 27 27
- 2.2.3.1 Programming Model 28
- HOST/SYSTEM VIEW 29
- PHYSICAL MEMORY 29
- (DRAM CONTROLLER VIEW) 29
- Datasheet, Volume 2 33 33
- 34 Datasheet, Volume 2 34
- 2.2.9 I/O Address Space 35
- 36 Datasheet, Volume 2 36
- Datasheet, Volume 2 37 37
- 2.4 Configuration Mechanisms 38
- Datasheet, Volume 2 39 39
- 40 Datasheet, Volume 2 40
- Datasheet, Volume 2 41 41
- 42 Datasheet, Volume 2 42
- Datasheet, Volume 2 43 43
- 2.6 I/O Mapped Registers 44
- 2.7.6 CC—Class Code Register 49
- TXT Lockable 54
- 1:0 to 11b 56
- 4) from 58
- B0h, bits 15:4) 58
- 2.8 MCHBAR Registers 66
- 00h RW 67
- Register Symbol Register Name 67
- 208–209h 73
- 20A–20Bh 74
- 24D–24Fh 74
- 250-251h 75
- 252–255h 76
- 256–257h 77
- 258–25Ah 77
- 269–26Eh 79
- 298–29Bh 82
- 29C–29Fh 84
- 2B4–2B7h 84
- 600–601h 86
- 602–603h 86
- 604–605h 86
- 64D–64Fh 88
- 650–651h 88
- 652–655h 89
- 656–657h 90
- 658–65Ah 90
- 660–663h 91
- 6B4–6B7h 93
- C20–C27h 94
- 1001–1002h 94
- 1004–1005h 95
- 101E–101Fh 100
- Register 107
- 10EC–10EDh 108
- 2C20–2C22h 109
- 2.9 EPBAR Registers 110
- 2.10 PCI Device 1 Registers 115
- PCI device 117
- Port Command Register 140
- 11:10 RW-O 11b 143
- OS's during run time 155
- 104–107h 156
- 108–10Bh 157
- 10C–10Dh 157
- 110–113h 158
- 23 RO 0b Reserved 158
- 114–117h 158
- 11A–11Bh 159
- 2.12 DMIBAR Registers 161
- Declaration Capability 169
- 2.13.6 CC—Class Code Register 177
- Range Address Register 179
- GMADR register 180
- 2.14 Device 2 I/O Registers 183
- 100–107h 211
- 108–10Fh 212
- 200–20Fh 214
- F00–F03h 215
- F04–F07h 216
- Dedication 217
- F08–F0Bh 218
- FFC–FFFh 219
- 2.16 DMI VC1 REMAP Registers 221
- 2.17.2 GFXPLL1—GFX PLL BIOS 254
- 2.18 GFXVTBAR Registers 255
- Address Register 281
- 2.19 PCI Device 6 Registers 288
- 2.19.45 RSTS—Root Status 327
- 2.21 Intel 332
- Specific Registers 332
- 110–117h 333
- 330–337h 333
- Lower Half Register 334
- Upper Half Register 334
- QuickPath Architecture 335
- System Address Decode 335
- Register Description 335
- QPI Link 0 Registers 340
- QPI Physical 0 Registers 341
- 3.4 PCI Standard Registers 342
- 3.4.4 CCR—Class Code Register 344
- Identification Register 345
- 3.4.7 PCICMD—Command Register 346
- 3.5.1 MAX_RTIDS 349
- 3.6.1 SAD_PAM0123 349
- 3.6.2 SAD_PAM456 351
- 3.6.3 SAD_HEN 352
- 3.6.4 SAD_SMRAM 353
- 3.6.5 SAD_PCIEXBAR 354
- 3.7 Intel 356
- QPI Link Registers 356
- 3.8 Intel 357
- QPI Physical Layer Registers 357
- 360 Datasheet, Volume 2 360
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