Datasheet, Volume 2 359
Intel
®
QuickPath Architecture System Address Decode Register Description
3.8.3 QPI_0_PH_PIS, QPI_1_PH_PIS
This is an Intel QPI Physical Layer Initialization Status Register.
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Device: 2
Function: 1
Offset: 80h
Access as a Dword
Bit Type
Reset
Value
Description
31:30 RV – Reserved
29 RO –
GLOBAL_ERROR
Set upon any error detected on the link during Loopback Pattern.
28 RO –
TEST_BUSY
Test busy bit indicating that a test is in progress.
27 RW1C 0
STATE_HOLD.
State machine hold bit for single step and init freeze modes.
26 RO –
INIT_SPEED. Current initialization speed.
1 = Operational Speed Initialization.
0 = Slow Speed Initialization.
25 RO – PORT_RMT_ACK. Port Remote ACK status.
24 RO – PORT_TX_RDY. Port Tx Ready status.
23:21 RV – Reserved
20:16 RO – RX_STATE. Current state of the local Rx.
15:13 RV – Reserved
12:8 RO – TX_STATE. Current state of the local Tx.
7:2 RV – Reserved
1RW1C0
CALIBRATION_DONE.
This bit indicates that calibration has been completed for the Intel QPI
link.
0RW1C0
LINKUP_IDENTIFIER. Link up identifier for the Intel QPI link.
Set to 0 during Default Reset.
Set to 1 when initialization completes and link enters L0.
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