Intel B940 Datasheet download pdf (Page 347)

Datasheet, Volume 2 347

Intel

QuickPath Architecture System Address Decode Register Description

3.4.8 PCISTS—PCI Status Register

The PCI Status register is a 16-bit status register that reports the occurrence of various

error events on this device's PCI interface.

Device: 0

Function: 0–1

Offset: 06h

Device: 2

Function: 0–1

Offset: 06h

Bit Type

Reset

Value

Description

15 RO 0

Detect Parity Error (DPE)

The host bridge does not implement this bit and is hard wired to a 0.

Writes to this bit position have no effect.

14 RO 0

Signaled System Error (SSE)

This bit is set to 1 when this device generates an SERR message over the

bus for any enabled error condition. If the host bridge does not signal

errors using this bit, this bit is hard wired to a “0” and is read-only. Writes

to this bit position have no effect.

13 RO 0

Received Master Abort Status (RMAS)

This bit is set when this device generates request that receives an

Unsupported Request completion packet. Software clears the bit by

writing 1 to it.

If this device does not receive Unsupported Request completion packets,

the bit is hard wired to “0” and is read-only. Writes to this bit position

have no effect.

12 RO 0

Received Target Abort Status (RTAS)

This bit is set when this device generates a request that receives a

Completer Abort completion packet. Software clears this bit by writing a 1

to it.

If this device does not receive Completer Abort completion packets, this

bit is hard wired to “0” and read-only. Writes to this bit position have no

effect.

11 RO 0

Signaled Target Abort Status (STAS)

This device will not generate a Target Abort completion or Special Cycle.

This bit is not implemented in this device and is hard wired to a 0. Writes

to this bit position have no effect.

10:9 RO 0

DEVSEL Timing (DEVT)

These bits are hard wired to “00”. Writes to these bit positions have no

effect. This device does not physically connect to any PCI bus. These bits

are set to “00” (fast decode) so that optimum DEVSEL timing for physical

PCI busses are not limited by this device.

8RO0

Master Data Parity Error Detected (DPD)

PERR signaling and messaging are not implemented by this bridge,

therefore this bit is hard wired to 0. Writes to this bit position have no

effect.

7RO1

Fast Back-to-Back (FB2B)

This bit is hard wired to 1. Writes to this bit position have no effect. This

device is not physically connected to a PCI bus. This bit is set to 1

(indicating back-to-back capabilities) so that the optimum setting for this

PCI bus is not limited by this device.

6RO0Reserved

5RO0

66 MHz Capable

Does not apply to PCI Express. Must be hard wired to 0.

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Intel B940 Datasheet Page 347

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