Intel B940 Datasheet download pdf (Page 315)

Datasheet, Volume 2 315

Processor Configuration Registers

2.19.38 LCAP—Link Capabilities Register

This register indicates PCI Express device specific capabilities.

B/D/F/Type: 0/6/0/PCI

Address Offset: AC–AFh

Reset Value: 03214C82h

Access: RO, RW-O

Bit Attr

Reset

Value

Description

31:24 RO 03h

Port Number (PN)

This field indicates the PCI Express port number for the given PCI Express

link. Matches the value in Element Self Description[31:24].

23:22 RO 00b Reserved

21 RO 1b

Link Bandwidth Notification Capability (LBNC)

A value of 1b indicates support for the Link Bandwidth Notification status and

interrupt mechanisms. This capability is required for all Root Ports and Switch

downstream ports supporting Links wider than x1 and/or multiple Link

speeds.

This field is not applicable and is reserved for Endpoint devices, PCI Express

to PCI/PCI-X bridges, and Upstream Ports of Switches.

Devices that do not implement the Link Bandwidth Notification capability

must hardwire this bit to 0b.

20 RO 0b

Data Link Layer Link Active Reporting Capable (DLLLARC)

For a Downstream Port, this bit must be set to 1b if the component supports

the optional capability of reporting the DL_Active state of the Data Link

Control and Management State Machine. For a hot-plug capable Downstream

Port (as indicated by the Hot-Plug Capable field of the Slot Capabilities

For Upstream Ports and components that do not support this optional

capability, this bit must be hardwired to 0b.

19 RO 0b

Surprise Down Error Reporting Capable (SDERC)

For a Downstream Port, this bit must be set to 1b if the component supports

the optional capability of detecting and reporting a Surprise Down error

condition.

For Upstream Ports and components that do not support this optional

capability, this bit must be hardwired to 0b.

18 RO 0b

Clock Power Management (CPM)

A value of 1b in this bit indicates that the component tolerates the removal of

any reference clock(s) when the link is in the L1 and L2/3 Ready link states.

A value of 0b indicates the component does not have this capability and that

reference clock(s) must not be removed in these link states.

This capability is applicable only in form factors that support "clock request"

(CLKREQ#) capability.

For a multi-function device, each function indicates its capability

independently. Power Management configuration software must only permit

reference clock removal if all functions of the multifunction device indicate a

1b in this bit.

17:15 RW-O 010b

L1 Exit Latency (L1ELAT)

Indicates the length of time this Port requires to complete the transition from

L1 to L0. The value 010 b indicates the range of 2 us to less than 4 us.

BIOS Requirement: If this field is required to be any value other than the

default,

BIOS must initialize it accordingly.

Both bytes of this register that contain a portion of this field must be written

simultaneously in order to prevent an intermediate (and undesired) value

from ever existing.

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Intel B940 Datasheet Page 315

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