Intel B940 Datasheet download pdf (Page 274)

Processor Configuration Registers

274 Datasheet, Volume 2

2.18.15 PLMBASE_REG—Protected Low Memory Base Register

This register is used to set up the base address of DMA-protected low-memory region

below 4 GB. This register must be set up before enabling protected memory through

PMEN_REG, and must not be updated when protected memory regions are enabled.

When the LT CMD.LOCK.PMRC command is invoked, this register is locked (treated as

RO). When the LT CMD.UNLOCK.PMRC command is invoked, this register is unlocked

(treated as RW). Refer to the VTd specification for security considerations.

This register is always treated as RO for implementations not supporting protected low

memory region (PLMR field reported as 0 in the Capability register).

The alignment of the protected low memory region base depends on the number of

reserved bits (N:0) of this register. Software may determine N by writing all 1s to this

the register. Bits N:0 of this register are decoded by hardware as all 0s.

Software must setup the protected low memory region below 4 GB. The VTd

specification describes the Protected Low-Memory Limit register and hardware

decoding of these registers.

B/D/F/Type: 0/2/0/GFXVTBAR

Address Offset: 68–6Bh

Reset Value: 00000000h

Access: RO, RW

Bit Attr

Reset

Value

Description

31:21 RW 000h

Protected Low-Memory Base (PLMB)

This register specifies the base of protected low-memory region in system

memory.

20:0 RO 000000h Reserved

1 2 ... 269 270 271 272 273 274 275 276 277 278 279 ... 359 360

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Intel B940 Datasheet Page 274