Intel B940 Datasheet download pdf (Page 241)

Datasheet, Volume 2 241

Processor Configuration Registers

2.16.17 PHMBASE_REG—Protected High-Memory Base Register

This register is used to set up the base address of DMA-protected high-memory region.

This register must be set up before enabling protected memory through PMEN_REG,

and must not be updated when protected memory regions are enabled.

This register is always treated as RO for implementations not supporting protected high

memory region (PHMR field reported as Clear in the Capability register).

The alignment of the protected high memory region base depends on the number of

reserved bits (N:0) of this register. Software may determine N by writing all 1s to this

in the value read back from the register. Bits N:0 of this register are decoded by

hardware as all 0s.

Software may setup the protected high memory region either above or below 4GB.

The VTd specification describes the Protected High-Memory Limit register and hardware

decoding of these registers.

Software must not modify this register when protected memory regions are enabled.

(PRS field Set in PMEN_REG).

B/D/F/Type: 0/0/0/DMIVC1REMAP

Address Offset: 70–77h

Reset Value: 0000000000000000h

Access: RW, RO

Bit Attr

Reset

Value

Description

63:21 RW

00000000

000h

Protected High-Memory Base (PHMB)

This register specifies the base of protected (high) memory region in system

memory.

Hardware ignores, and does not implement, bits 63:HAW, where HAW is the

host address width.

20:0 RO 000000h Reserved

1 2 ... 236 237 238 239 240 241 242 243 244 245 246 ... 359 360

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Intel B940 Datasheet Page 241