Intel B940 Datasheet download pdf (Page 228)

Processor Configuration Registers

228 Datasheet, Volume 2

28 W 0b

Enable Advanced Fault Logging (EAFL)

This field is valid only for implementations supporting advanced fault logging.

Software writes to this field to request hardware to enable or disable

advanced fault logging.

0 = Disable advanced fault logging. In this case, translation faults are

reported through the Fault Recording registers.

1 = Enable use of memory-resident fault log. When enabled, translation

faults are recorded in the memory-resident log. The fault log pointer

must be set in hardware (through SFL field) before enabling advanced

fault logging.

Hardware reports the status of the advanced fault logging enable operation

through the AFLS field in the Global Status register.

Value returned on read of this field is undefined.

27 W 0b

Write Buffer Flush (WBF)

This bit is valid only for implementations requiring write buffer flushing.

Software sets this field to request hardware to flush the root-complex

internal write buffers. This is done to ensure any updates to the memory-

resident DMA-remapping structures are not held in any internal write posting

buffers. Refer to the VTd specification for details on write-buffer flushing

requirements.

Hardware reports the status of the write buffer flushing operation through

the WBFS field in the Global Status register.

Clearing this bit has no effect.

Value returned on read of this field is undefined.

26 RO 0b

Queued Invalidation Enable (QIE)

This field is valid only for implementations supporting queued invalidations.

Software writes to this field to enable or disable queued invalidations.

0 = Disable queued invalidations.

1 = Enable use of queued invalidations.

Hardware reports the status of queued invalidation enable operation through

QIES field in the Global Status register.

Refer to the VTd specification for software requirements for

enabling/disabling queued invalidations.

The value returned on a read of this field is undefined.

25 RO 0b

Interrupt Remapping Enable (IRE)

This field is valid only for implementations supporting interrupt remapping.

0 = Disable interrupt-remapping hardware

1 = Enable interrupt-remapping hardware

Hardware reports the status of the interrupt remapping enable operation

through the IRES field in the Global Status register.

There may be active interrupt requests in the platform when software

updates this field. Hardware must enable or disable interrupt-remapping logic

only at deterministic transaction boundaries, so that any in-flight interrupts

are either subject to remapping or not at all.

Hardware implementations must drain any in-flight interrupts requests

queued in the Root-Complex before completing the interrupt-remapping

enable command and reflecting the status of the command through the IRES

field in the Global Status register.

The value returned on a read of this field is undefined.

B/D/F/Type: 0/0/0/DMIVC1REMAP

Address Offset: 18–1Bh

Reset Value: 00000000h

Access: W, RO

Bit Attr

Reset

Value

Description

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Intel B940 Datasheet Page 228

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