Intel B940 Datasheet download pdf (Page 184)

Processor Configuration Registers

184 Datasheet, Volume 2

2.14.1 Index—MMIO Address Register

A 32 bit I/O write to this port loads the offset of the MMIO register or offset into the

GTT that needs to be accessed. An I/O Read returns the current value of this register.

An 8/16 bit I/O write to this register is completed by the processor but does not update

this register.

This mechanism to access internal graphics MMIO registers must not be used to access

VGA IO registers which are mapped through the MMIO space. VGA registers must be

accessed directly through the dedicated VGA I/O ports.

2.14.2 Data—MMIO Data Register

A 32 bit IO write to this port is re-directed to the MMIO register/GTT location pointed to

by the MMIO-index register. A 32 bit IO read to this port is re-directed to the MMIO

selection in MMIO_INDEX(1:0). 8 or 16 bit IO writes are completed by the processor

and may have un-intended side effects, hence must not be used to access the data

port. 8 or 16 bit IO reads are completed normally.

Note that if the target field in MMIO Index selects "GTT", reads to MMIO data return is

undefined.

B/D/F/Type: 0/2/0/PCI IO

Address Offset: 0–3h

Reset Value: 0000_0000h

Access: RW

Bit Attr

Reset

Value

Description

31:2 RW

00000000

This field selects any one of the DWORD registers within the MMIO register

space of Device 2 if the target is MMIO Registers.

This field selects a GTT offset if the target is the GTT.

1:0 RO 0h Reserved

B/D/F/Type: 0/2/0/PCI IO

Address Offset: 4–7h

Reset Value: 0000_0000h

Access: RW

Bit Attr

Reset

Value

Description

31:0 RW 00000000

MMIO Data Window (DATA)

1 2 ... 179 180 181 182 183 184 185 186 187 188 189 ... 359 360

No comments

Intel B940 Datasheet Page 184