Processor Configuration Registers
182 Datasheet, Volume 2
2.13.14 SID2—Subsystem Identification Register
2.13.15 ROMADR—Video BIOS ROM Base Address Register
The IGD does not use a separate BIOS ROM, therefore this register is hardwired to 0s.
2.13.16 INTRPIN—Interrupt Pin Register
B/D/F/Type: 0/2/0/PCI
Address Offset: 2E–2Fh
Reset Value: 0000h
Access: RW-O
Bit Attr
Reset
Value
Description
15:0 RW-O 0000h
Subsystem Identification (SUBID)
This value is used to identify a particular subsystem. This field should be
programmed by BIOS during boot-up. Once written, this register becomes
Read Only. This register can only be cleared by a Reset.
B/D/F/Type: 0/2/0/PCI
Address Offset: 30–33h
Reset Value: 0000_0000h
Access: RO
Bit Attr
Reset
Value
Description
31:18 RO 0000h
ROM Base Address (RBA)
Hardwired to 0s.
17:11 RO 00h
Address Mask (ADMSK)
Hardwired to 0s to indicate 256 KB address range.
10:1 RO 000h
Reserved
Hardwired to 0s.
0RO 0b
ROM BIOS Enable (RBE)
0 = ROM not accessible.
B/D/F/Type: 0/2/0/PCI
Address Offset: 3Dh
Reset Value: 01h
Access: RO
Bit Attr
Reset
Value
Description
7:0 RO 01h
Interrupt Pin (INTPIN)
As a single function device, the IGD specifies INTA# as its interrupt pin.
01h = INTA#.
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