Intel SL22T Specifications Page 5

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1-3
INTRODUCTION
1.4 REFERENCES
Intel
®
64 and IA-32 Architectures Software Developer’s Manual (in five volumes)
http://developer.intel.com/products/processor/manuals/index.htm
Intel Virtualization Technology for Directed I/O, Rev 1.1 specification
http://download.intel.com/technology/computing/vptech/Intel(r)_VT_for_Direc
t_IO.pdf
Detecting Multi-Core Processor Topology in an IA-32 Platform
http://www3.intel.com/cd/ids/developer/asmo-na/eng/recent/275339.htm
The ACPI 4.0 specification
http://www.acpi.info/spec.htm
APIC ID
A unique ID that can identify individual agent in a platform (or clustered
configuration). The maximum bit-width supported is 8 bit, versus 32 bits
in x2APIC.
local xAPIC ID
The value configured in the local APIC ID register in xAPIC mode. This is an
8-bit value for xAPIC, and x2APIC in xAPIC mode. Because this is used to
specify a target destination in physical delivery mode, it is also referred to
as physical xAPIC ID. The processor initializes local xAPIC ID.
physical xAPIC ID See “local xAPIC ID”.
logical xAPIC ID
The APIC ID value that specifies a target processor to receive interrupt
delivered in logical destination mode in a local xAPIC. See documentation
on logical destination register (LDR) in Section 2.4.2. This is an 8-bit value.
Logical xAPIC ID is not initialized by hardware.
initial APIC ID
The value reported by CPUID.01H:EBX[31:24]. Initial APIC ID is initialized
by hardware.
x2APIC ID
The 32-bit value in the local APIC ID register defined by the x2APIC
architecture. The value is initialized by hardware and can be accessed via
RDMSR in x2APIC mode. It is also reported by CPUID.0BH:EDX. Application
can query CPUID.0BH:EDX in user mode without RDMSR.
logical x2APIC ID
The APIC ID value that specifies a target processor to receive interrupt
delivered in logical destination mode in a local x2APIC. This is a 32-bit
value initialized by hardware.
RsvdZ Reads of reserved bits return zero
Table 1-1. Description of terminology
Term Description
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