Intel SL22T Specifications download pdf (Page 4)

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INTRODUCTION

However no modifications are required to PCI or PCIe devices that support direct

interrupt delivery to the processors via Message Signaled Interrupts. Similarly no

modifications are required to the IOxAPIC. The routing of interrupts from these

devices in x2APIC mode leverages the interrupt remapping architecture specified in

the Intel Virtualization Technology for Directed I/O, Rev 1.1 specification.

Modifications to ACPI interfaces to support x2APIC are described in the ACPI 4.0

specification.

1.3 GLOSSARY

This document uses the terms listed in the following table.

Table 1-1. Description of terminology

Term Description

APIC

The set of advanced programmable interrupt controller features which

may be implemented in a stand-alone controller, part of a system chipset,

or in a microprocessor.

local APIC

The processor component that implements the APIC functionalities. The

underlying APIC registers their functionalities are documented in Chapter

8 of “Intel® 64 and IA-32 Architectures Software Developer’s Manual“, Vol.

3B. Historically, this may refer narrowly to early generations of processor

component in the Pentium and P6 processors. In this document, we also

use this term generically across multiple generations of processor

components.

I/O APIC

The system chipset component that implements APIC functionalities to

communicate with a local APIC.

xAPIC

The extension of the APIC architecture that includes messaged APIC

interface over the system bus and expanding processor physical

addressability from 4 bits to 8 bits.

local xAPIC

The processor component that implements the associated xAPIC

functionalities. This is supported by Intel® Pentium® 4 processors,

Pentium® M processors, Intel® Core

2 Duo processors, and Intel® Xeon®

processors based on Intel® NetBurst microarchitecture and Intel® Core

microarchitecture.

x2APIC

The extension of xAPIC architecture to support 32 bit addressability of

processors and associated enhancements.

local x2APIC

The processor component that implements the associated x2APIC

functionalities.

xAPIC mode

The operating mode of a local xAPIC unit when it is enabled, or that of a

local x2APIC unit when it is enabled but not in extended mode.

x2APIC mode

The operating mode of a local x2APIC unit when it is enabled and in

extended mode.

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