Intel SL22T Specifications download pdf (Page 12)

2-6

LOCAL X2APIC ARCHITECTURE

2.3.3 Reserved Bit Checking

Section 2.3.2 and Table 2-2 specifies the reserved bit definitions for the APIC regis-

ters in x2APIC mode. Non-zero writes (by WRMSR instruction) to reserved bits to

these registers will raise a general protection fault exception while reads return zeros

(RsvdZ semantics).

0320H 032H LVT Timer Register Read/Write.

0330H 033H LVT Thermal Sensor

Read/Write.

0340H 034H LVT Performance

Monitoring Register

Read/Write.

0350H 035H LVT LINT0 Register Read/Write.

0360H 036H LVT LINT1 Register Read/Write.

0370H 037H LVT Error Register Read/Write.

0380H 038H Initial Count Register

(for Timer)

Read/Write.

0390H 039H Current Count Register

(for Timer)

Read Only.

03A0H-

03D0H

03AH-03DH Reserved

03E0H 03EH Divide Configuration

Read/Write.

Not supported 03FH SELF IPI

Write only Only in x2APIC mode

040H-3FFH Reserved

NOTES:

1. Destination format register (DFR) is supported in xAPIC mode at

MMIO offset 00E0H.

2. APIC register at MMIO offset 0310H is accessible in xAPIC mode

only

3. MSR 831H (offset 31H) is reserved; read/write operations will result

in a GP fault.

4. SELF IPI register is supported only if x2APIC mode is enabled.

Table 2-2. Local APIC Register Address Map Supported by x2APIC (Contd.)

MMIO Offset

(xAPIC mode)

MSR Offset

(x2APIC

mode) Register Name

R/W

Semantics Comments

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 ... 34 35

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Intel SL22T Specifications Page 12

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