Intel SL22T Specifications download pdf (Page 14)

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LOCAL X2APIC ARCHITECTURE

Other semantics change related to reading/writing the ICR in x2APIC mode vs. xAPIC

mode are:

• Completion of the WRMSR instruction to the ICR does not guarantee that the

interrupt to be dispatched has been received by the targeted processors. If the

system software usage requires this guarantee, then the system software should

explicitly confirm the delivery of the interrupt to the specified targets using an

alternate software mechanisms. For example, one possible mechanism would be

having the interrupt service routine associated with the target interrupt delivery

to update a memory location, thereby allowing the dispatching software to verify

the memory location has been updated.

• A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both

logical destination and physical destination modes.

• The Delivery Status bit of the ICR has been removed. Software need not poll on

the Delivery Status bit before writing the ICR.

• ICR reads are still allowed to aid debugging. However software should not

assume the value returned by reading the ICR is the last written value.

2.3.5.2 Task Priority Register Semantics

In x2APIC mode, the layout of the Task Priority Register has the same layout as in the

xAPIC mode.

The semantics for reading and writing to the TPR register via the MSR interface are

identical to those used for TPR access via the CR8 register. Specifically, the write to

the TPR register ensures that the result of any re-prioritization action due to the

change in processor priority is reflected to the processor prior to the next instruction

following the TPR write. Any deliverable interrupts resulting from the TPR write would

be taken at the instruction boundary following the TPR write.

2.3.5.3 End Of Interrupt Register Semantics

In xAPIC mode, the EOI register is written by an interrupt service routine to indicate

that the current interrupt service has completed. System software performs a write

to the EOI register to signal an EOI.

In the x2APIC mode, the write of a zero value to EOI register is enforced. Writes of a

non-zero value to the EOI register in x2APIC mode will raise a GP fault. System soft-

ware continues to have to perform the EOI write to indicate interrupt service comple-

tion. But in x2APIC mode, the EOI write is with a value of zero.

2.3.5.4 Error Status Register Semantics

The Error Status register (ESR) records all errors detected by the local APIC. In

xAPIC mode, software can read/write to the ESR. A write (of any value) to the ESR

must be done to update the register before attempting to read it. This write clears

any previously logged errors and updates the ESR with any errors detected since the

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Intel SL22T Specifications Page 14