Intel SL22T Specifications download pdf (Page 18)

2-12

LOCAL X2APIC ARCHITECTURE

In the xAPIC mode, the Destination Format Register (DFR) through MMIO interface

determines the choice of a flat logical mode or a clustered logical mode. Flat logical

mode is not supported in the x2APIC mode. Hence the Destination Format Register

(DFR) is eliminated in x2APIC mode.

The 32-bit logical x2APIC ID field of LDR is partitioned into two sub-fields:

• Cluster ID (LDR[31:16]): is the address of the destination cluster

• Logical ID (LDR[15:0]): defines a logical ID of the individual local x2APIC within

the cluster specified by LDR[31:16].

This layout enables 2^16-1 clusters each with up to 16 unique logical IDs - effec-

tively providing an addressability of ((2^20) - 16) processors in logical destination

mode.

It is likely that processor implementations may choose to support less than 16 bits of

the cluster ID or less than 16-bits of the Logical ID in the Logical Destination Register.

However system software should be agnostic to the number of bits implemented in

the cluster ID and logical ID sub-fields. The x2APIC hardware initialization will ensure

that the appropriately initialized logical x2APIC IDs are available to system software

and reads of non-implemented bits return zero. This is a read-only register that soft-

ware must read to determine the logical x2APIC ID of the processor. Specifically,

software can apply a 16-bit mask to the lowest 16 bits of the logical x2APIC ID to

identify the logical address of a processor within a cluster without needing to know

the number of implemented bits in cluster ID and Logical ID sub-fields. Similarly,

software can create a message destination address for cluster model, by bit-Oring

the Logical X2APIC ID (31:0) of processors that have matching Cluster ID(31:16).

To enable cluster ID assignment in a fashion that matches the system topology char-

acteristics and to enable efficient routing of logical mode lowest priority device inter-

rupts in link based platform interconnects, the LDR are initialized by hardware based

on the value of x2APIC ID upon x2APIC state transitions. Details of this initialization

are provided in Section 2.4.4.

Figure 2-4. Logical Destination Register in x2APIC Mode

MSR Address: 80DH

31 0

Logical x2APIC ID

1 2 ... 13 14 15 16 17 18 19 20 21 22 23 ... 34 35

No comments

Intel SL22T Specifications Page 18