Intel SL22T Specifications Page 1

iIntel® 64 Architecture x2APICSpecificationReference Number: 318148-004March 2010

2-4LOCAL X2APIC ARCHITECTURE• The SELF IPI register is available only if x2APIC mode is enabled.The MSR address space is compressed to allow for futur

2-5LOCAL X2APIC ARCHITECTURE0120H 012H ISR bits 64:95 Read Only.0130H 013H ISR bits 96:127 Read Only.0140H 014H ISR bits 128:159 Read Only.0150H 015H

2-6LOCAL X2APIC ARCHITECTURE2.3.3 Reserved Bit CheckingSection 2.3.2 and Table 2-2 specifies the reserved bit definitions for the APIC regis-ters in x

2-7LOCAL X2APIC ARCHITECTURE2.3.4 Error HandlingRDMSR and WRMSR operations to reserved addresses in the x2APIC mode will raise a GP fault. (Note: In x

2-8LOCAL X2APIC ARCHITECTUREOther semantics change related to reading/writing the ICR in x2APIC mode vs. xAPIC mode are: • Completion of the WRMSR ins

2-9LOCAL X2APIC ARCHITECTURElast write to the ESR. Errors are collected regardless of LVT Error mask bit, but the APIC will only issue an interrupt d

2-10LOCAL X2APIC ARCHITECTURE2.3.7 VM-exit Controls for MSRs and x2APIC RegistersThe VMX architecture allows a VMM to specify lists of MSRs to be loa

2-11LOCAL X2APIC ARCHITECTUREthan 32 bits in its hardware. System software should be agnostic to the actual number of bits that are implemented. All n

2-12LOCAL X2APIC ARCHITECTUREIn the xAPIC mode, the Destination Format Register (DFR) through MMIO interface determines the choice of a flat logical m

2-13LOCAL X2APIC ARCHITECTURE2.4.3 Interrupt Command Register In x2APIC mode, the layout of the Interrupt Command Register is shown in Figure 2-5. Th

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2-14LOCAL X2APIC ARCHITECTUREdebugging; however, software should not assume the value returned by reading the ICR is the last written value.A destinat

2-15LOCAL X2APIC ARCHITECTUREThe SELF IPI register is a write-only register. A RDMSR instruction with address of the SELF IPI register will raise a GP

2-16LOCAL X2APIC ARCHITECTUREDirected EOI capability is intended to enable system software to perform directed EOIs to specific IOxAPICs in the system

2-17LOCAL X2APIC ARCHITECTUREx2APIC modes of a local x2APIC unit. Layout of the Local APIC Version register is as shown in Figure 2-8. The Directed EO

2-18LOCAL X2APIC ARCHITECTURE• The local APIC ID is initialized by hardware with a 32 bit ID (x2APIC ID). The lowest 8 bits of the x2APIC ID is the le

2-19LOCAL X2APIC ARCHITECTURE2.7.1.1 x2APIC After RESETThe valid transitions from the xAPIC mode state are:• to the x2APIC mode by setting EXT to 1 (r

2-20LOCAL X2APIC ARCHITECTUREA RESET in the disabled state places the x2APIC in the xAPIC mode. All APIC registers (including the local APIC ID regist

2-21LOCAL X2APIC ARCHITECTUREprocessor topology. The relevant information in CPUID leaves 01H and 04H do not directly map to individual levels of the

2-22LOCAL X2APIC ARCHITECTUREThe lowest level number is zero. Level number = 0 is reserved to specify SMT-related topology information (see Hyper-Thre

2-23LOCAL X2APIC ARCHITECTURE2.8.1 Consistency of APIC IDs and CPUIDThe consistency of physical x2APIC ID in MSR 802H in x2APIC mode and the 32-bit v

1-1INTRODUCTIONCHAPTER 1INTRODUCTION1.1 INTRODUCTIONThe xAPIC architecture provided a key mechanism for interrupt delivery in many generations of Inte

2-24LOCAL X2APIC ARCHITECTURE• Re-directible/Lowest Priority inter-processor interrupts are not supported in the x2APIC architecture.

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2-26LOCAL X2APIC ARCHITECTURE

Index-1INDEXAAPIC. . . . . . . . . . . . . . . . . . . . . . . 1, 2, 1, 6, 7, 9, 17APIC ID. . . . . . . . . . . . . . . . . . . . . . . . . 3, 11, 14,

Index-2SSELF IPI register . . . . . . . . . . . . . . . . . . . . . . . . 4, 7SVRSpurious Interrupt Vector Register . . . . . . . . . 16TTMRTrigger M

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1-2INTRODUCTIONHowever no modifications are required to PCI or PCIe devices that support direct interrupt delivery to the processors via Message Signa

1-3INTRODUCTION1.4 REFERENCES• Intel® 64 and IA-32 Architectures Software Developer’s Manual (in five volumes)http://developer.intel.com/products/proc

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2-1LOCAL X2APIC ARCHITECTURECHAPTER 2LOCAL X2APIC ARCHITECTURE2.1 X2APIC ENHANCEMENTSThe key enhancements provided by the x2APIC architecture over xA

2-2LOCAL X2APIC ARCHITECTURE2.2 DETECTING AND ENABLING X2APICA processor’s support to operate its local APIC in the x2APIC mode can be detected by qu

2-3LOCAL X2APIC ARCHITECTUREbit 10 to zero. Section 2.7, “x2APIC STATE TRANSITIONS” provides a detailed state diagram for the state transitions allowe