Intel SL22T Specifications download pdf (Page 23)

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LOCAL X2APIC ARCHITECTURE

x2APIC modes of a local x2APIC unit. Layout of the Local APIC Version register is as

shown in Figure 2-8. The Directed EOI feature is supported if bit 24 is set to 1.

2.6 INTERACTION WITH PROCESSOR CORE OPERATING

MODES

Similar to the xAPIC architecture, the APIC registers defined in the x2APIC architec-

ture are accessible in the following operating modes of the processor: Protected

Mode, Virtual-8086 Mode, Real Mode, and IA-32e mode (both 64-bit and compati-

bility sub-modes).

2.7 X2APIC STATE TRANSITIONS

This section provides a detailed description of the x2APIC states of a local x2APIC

unit, transitions between these states as well as interactions of these states with INIT

and RESET.

2.7.1 x2APIC States

The valid states for a local x2APIC unit is listed in Table 2-1:

• APIC disabled: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=0

• xAPIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=0

• x2APIC mode: IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=1

• Invalid: IA32_APIC_BASE[EN]=0 and IA32_APIC_BASE[EXTD]=1

The state corresponding to EXTD=1 and EN=0 is not valid and it is not possible to get

into this state. Values written to the IA32_APIC_BASE_MSR that attempt a transition

from a valid state to this invalid state will cause a GP fault. Figure 2-9 shows the

comprehensive state transition diagram for a local x2APIC unit.

On coming out of RESET, the local x2APIC unit is enabled and is in the xAPIC mode:

IA32_APIC_BASE[EN]=1 and IA32_APIC_BASE[EXTD]=0. The APIC registers are

initialized as:

Figure 2-8. Local APIC Version Register of x2APIC

Reserved

23 15

MMIO Address: FEE0 0030H

MSR Address: 0803H

Directed EOI Support

Reserved

Vector

Max LVT Entry

1 2 ... 18 19 20 21 22 23 24 25 26 27 28 ... 34 35

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Intel SL22T Specifications Page 23