Intel SL22T Specifications download pdf (Page 20)

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LOCAL X2APIC ARCHITECTURE

debugging; however, software should not assume the value returned by reading the

ICR is the last written value.

A destination ID value of FFFF_FFFFH is used for broadcast of interrupts in both

logical destination and physical destination modes.

2.4.4 Deriving Logical x2APIC ID from the Local x2APIC ID

In x2APIC mode, the 32-bit logical x2APIC ID, which can be read from LDR, is derived

from the 32-bit local x2APIC ID. Specifically, the 16-bit logical ID sub-field is derived

by shifting 1 by the lowest 4 bits of the x2APIC ID, i.e. Logical ID = 1 << x2APIC

ID[3:0]. The rest of the bits of the x2APIC ID then form the cluster ID portion of the

logical x2APIC ID:

Logical x2APIC ID = [(x2APIC ID[31:4] << 16) | (1 << x2APIC ID[3:0])]

The use of lowest 4 bits in x2APIC ID implies that at least 16 APIC IDs are reserved

for logical processors within a socket in multi-socket configurations. If more than 16

APIC IDS are reserved for logical processors in a socket/package then multiple

cluster IDs can exist within the package.

The LDR initialization occurs whenever the x2APIC mode is enabled. This is described

in Section 2.7.

2.4.5 SELF IPI register

SELF IPIs are used extensively by some system software. The xAPIC architecture

provided a mechanism for sending an IPI to the current local APIC using the "self-IPI"

short-hand in the interrupt command register (see Figure 2-5). The x2APIC architec-

ture introduces a new register interface. This new register is dedicated to the

purpose of sending self-IPIs with the intent of enabling a highly optimized path for

sending self-IPIs.

Figure 2-6 provides the layout of the SELF IPI register. System software only speci-

fies the vector associated with the interrupt to be sent. The semantics of sending a

self-IPI via the SELF IPI register are identical to sending a self targeted edge trig-

gered fixed interrupt with the specified vector. Specifically the semantics are identical

to the following settings for an inter-processor interrupt sent via the ICR - Destina-

tion Shorthand (ICR[19:18] = 01 (Self)), Trigger Mode (ICR[15] = 0 (Edge)),

Delivery Mode (ICR[10:8] = 000 (Fixed)), Vector (ICR[7:0] = Vector).

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Intel SL22T Specifications Page 20